PCB Layout Design for PCA9685 Servo Controller
Thought
Work done
- Created and populated the project specification: Project Specification.
- Renamed the project to Pi Nucleo PCA9685 Servo Controller and set the project description.
- Added the core schematic parts: 2× PCA9685PW, 1× TXS0102DQER, Raspberry Pi 40-pin header, STM32 Nucleo header, 17 servo headers, 5.1 V and 6.0 V power terminals, 17× 220 Ω PWM series resistors, OE 10 kΩ pull-up, VSENSE divider resistors, and rail/IC capacitors.
- Verified datasheets: TXS0102 includes internal 10 kΩ pull-ups on A/B I/O pins, so the optional external 4.7 kΩ I2C pull-ups were intentionally not added; PCA9685 OE is active-low, so the 10 kΩ pull-up implements the requested default-disabled servo safety behavior.
- ✅ Component set selected and added to schematic.
- ✅ Datasheet decisions captured for TXS0102 pull-ups and PCA9685 OE/address behavior.
- ❌ Schematic wiring is not complete yet.
- ❌ 4-layer stackup, 2 oz copper layout rules, placement, routing, and ERC/DRC validation are not complete.
- Wire all nets: Pi 3.3 V I2C → TXS0102 A-side, TXS0102 B-side → PCA9685 + Nucleo I2C, OE safety net, PCA9685 addresses, 17 PWM resistor chains, servo +6 V/GND rails, decoupling, and VSENSE divider.
- Then proceed to PCB layout: configure 4-layer/2 oz stackup, size the board, place components, route power/signal nets, and review ERC/DRC.
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Project Specification
Goal
Design a 4-layer, 2 oz copper PCB for a dual-PCA9685 servo controller integrating a Raspberry Pi 5 GPIO header and an STM32 Nucleo interface.
Electrical Requirements
- Raspberry Pi 5 I2C side: 3.3 V SDA/SCL into TXS0102 A-side.
- TXS0102 high side: 5.1 V logic rail, B1 = SDA_5V, B2 = SCL_5V.
- PCA9685 chip 1 address 0x40: all address pins tied to GND.
- PCA9685 chip 2 address 0x41: A0 tied to 5.1 V, remaining address pins tied to GND.
- PCA9685 VCC: 5.1 V logic rail.
- PCA9685 V+: 6.0 V servo power rail.
- PWM outputs: 17 total, each with a 220 ohm series resistor.
- OE safety line: STM32 Nucleo PC7/D9 drives OE; 10k pull-up to 5.1 V keeps outputs disabled by default.
- STM32 Nucleo interface: PB8/D15 = SCL_5V, PB9/D14 = SDA_5V, PC7/D9 = OE, PA0/A0 = VSENSE, 5V pin = 5.1 V logic input/reference, GND common.
- Voltage sense: 6.0 V servo rail divided to PA0/A0 with 10k/10k divider, producing approximately 3.0 V at nominal 6.0 V.
Physical Requirements
- 4-layer board.
- 2 oz / 70 um copper target for 20 A servo load paths.
- Use solid ground plane on layer 2 and power distribution on layer 3 where possible.
- High-current 6 V servo rail should use pours/planes rather than narrow traces.
Datasheet Review Notes
- Verify TXS0102 pull-up requirements before installing optional 4.7k I2C pull-ups.
- Verify PCA9685 OE active polarity and address-pin mapping before final review.
Implementation Choices
- Use NXP PCA9685PW TSSOP-28 for both PWM controllers.
- Use TI TXS0102 level translator.
- Use individual 1x3 servo headers for 17 outputs to preserve signal/+6V/GND grouping per connector.
Goal
Electrical Requirements
Physical Requirements
Datasheet Review Notes
Implementation Choices
