PCB Cleanup Blocked
Worked for 4 mins 24 sec
No changes made. HV Board inspected.
- Requested nets
ZMPT_SECONDARY_SIG:
- T1 pin 4
- Net portal present: T1 4 - R_VS1 P1
- No second real component pad on this HV board net.
V_SENSE:
- J_LINK pin 10
- Net portal present: U_COND INB- - D_CLAMP_V A
- No second real component pad on this HV board net.
VBIAS_1V65:
- T1 pin 3
- Net portal present: R_CBIAS1 P2 - R_CBIAS2 P1
- No second real component pad on this HV board net.
- T1 ZMPT101B pin nets
T1 pin 1: ZMPT_PRIMARY_A
T1 pin 2: ZMPT_PRIMARY_B
T1 pin 3: VBIAS_1V65
T1 pin 4: ZMPT_SECONDARY_SIG
- Nets with only one real component pad plus a net portal
These look like broken cross-board connections that can pass DRC while carrying no real local signal:
+5V:
- Real pad: J_LINK pin 4
- No other real component pad on this HV board net.
V_SENSE:
- Real pad: J_LINK pin 10
- Portal: U_COND INB- - D_CLAMP_V A
VBIAS_1V65:
- Real pad: T1 pin 3
- Portal: R_CBIAS1 P2 - R_CBIAS2 P1
ZMPT_SECONDARY_SIG:
- Real pad: T1 pin 4
- Portal: T1 4 - R_VS1 P1
Fix HV split nets
Restore ZMPT sensing
Handle unused +5V
Review split architecture
Run HV checks
Refine this doc
Ask about this doc
PCB Placement Bounds and Overlap Audit
Date: 2026-07-09
Scope: placement-only cleanup and audit. No routing was performed in this step.
Summary
- Board outline: 180 mm x 120 mm, centered at origin; board extents X = -90 to +90 mm, Y = -60 to +60 mm.
- Isolation keep-out: X = 6.5 to 8.5 mm, Y = -50 to +50 mm, on top and bottom layers.
- Right-edge cleanup completed: aggregate component bounds after cleanup are X = -89.40 to +89.90 mm, Y = -55.41 to +57.33 mm.
- Non-routing DRC after cleanup: overlapping copper = 0, floating copper = 0, dangling traces = 0, component outside board = 0, component body overlap = 0 open items, protected intrusions = 0.
- Remaining DRC: 158 expected airwire errors because the board is intentionally unrouted.
- Congestion note from layout analysis remains: router reports the LTE/MCU area as unroutable/congested near X ~= 63 mm, Y ~= 23-33 mm. This is a routing-congestion warning, not a non-routing DRC error.
Component Bounds Table
All units are mm. Bounds are computed from center and footprint/courtyard width/height returned by the layout inspection.
Table
| Ref | Center X | Center Y | Min X | Max X | Min Y | Max Y |
|---|---|---|---|---|---|---|
| C_3V3 | 50.00 | 20.00 | 48.77 | 51.23 | 19.49 | 20.51 |
| J_PWR | -84.00 | 52.00 | -88.78 | -79.22 | 46.67 | 57.33 |
| J_NEUTRAL | -84.00 | 4.00 | -88.78 | -79.22 | -1.33 | 9.33 |
| R_BASE3 | -12.00 | -37.00 | -13.37 | -10.63 | -41.61 | -32.39 |
| R_VS1 | 87.00 | 19.00 | 85.78 | 88.22 | 18.48 | 19.52 |
| K2 | -40.00 | 0.00 | -62.01 | -17.99 | -9.25 | 9.25 |
| D1 | -14.00 | 34.00 | -20.18 | -7.82 | 32.65 | 35.35 |
| U_COND | 26.00 | -20.00 | 22.32 | 29.68 | -22.87 | -17.13 |
| C_4V_IN | 74.00 | -18.00 | 72.78 | 75.22 | -18.51 | -17.49 |
| C_SIM_CLK | 84.00 | 14.00 | 82.78 | 85.22 | 13.49 | 14.51 |
| R_BASE1 | -12.00 | 36.00 | -13.37 | -10.63 | 31.39 | 40.61 |
| R_BIAS2 | 31.98 | -50.00 | 31.46 | 32.51 | -51.23 | -48.77 |
| MOV3 | -70.00 | -41.00 | -77.00 | -63.00 | -44.50 | -37.50 |
| R_SNUB3 | -70.00 | -47.00 | -72.03 | -67.97 | -47.91 | -46.09 |
| R_BIAS1 | 24.00 | -10.00 | 23.48 | 24.52 | -11.22 | -8.78 |
| J_DELTA | -84.00 | 16.00 | -88.78 | -79.22 | 10.67 | 21.33 |
| R_BURDEN | -60.00 | 19.00 | -62.02 | -57.98 | 18.09 | 19.91 |
| D_STATUS | 76.00 | -23.00 | 74.39 | 77.61 | -23.73 | -22.27 |
| L_EMI | 87.00 | 44.00 | 85.77 | 88.23 | 43.52 | 44.48 |
| U_OPTO1 | 7.50 | -44.00 | 2.69 | 12.31 | -46.53 | -41.47 |
| R_SNUB1 | -70.00 | 29.00 | -72.03 | -67.97 | 28.09 | 29.91 |
| J_S2 | -84.00 | -48.00 | -88.78 | -79.22 | -53.33 | -42.67 |
| C_CS | 14.00 | -36.78 | 13.49 | 14.51 | -38.01 | -35.55 |
| C_SNUB1 | -70.00 | 45.00 | -76.25 | -63.75 | 42.25 | 47.75 |
| J_UART | 86.80 | -34.00 | 85.00 | 88.60 | -38.33 | -29.68 |
| R_FB_TOP | 66.00 | -31.00 | 65.47 | 66.53 | -32.23 | -29.77 |
| C_VDD1 | 54.00 | -7.00 | 52.77 | 55.23 | -7.51 | -6.49 |
| D_CLAMP_V | 35.09 | -37.40 | 33.94 | 36.24 | -39.60 | -35.20 |
| MOV2 | -70.00 | -3.00 | -77.00 | -63.00 | -6.50 | 0.50 |
| J_ANT | 86.50 | 52.00 | 84.70 | 88.30 | 50.42 | 53.58 |
| C_VBAT | 67.00 | -6.00 | 65.78 | 68.22 | -6.51 | -5.49 |
| C_VCC | 54.00 | -26.00 | 52.77 | 55.23 | -26.51 | -25.49 |
| R_BOOT0 | 70.00 | -12.00 | 69.47 | 70.53 | -13.22 | -10.78 |
| U_3V3 | 37.00 | 12.53 | 32.85 | 41.15 | 9.12 | 15.94 |
| R_PWRKEY_PU | 65.00 | 20.00 | 64.47 | 65.53 | 18.77 | 21.23 |
| Q1 | -14.00 | 43.00 | -17.44 | -10.56 | 41.01 | 44.99 |
| R_SC1 | 18.00 | -12.00 | 16.77 | 19.23 | -12.53 | -11.47 |
| C_COND | 38.91 | -20.63 | 38.40 | 39.42 | -21.86 | -19.40 |
| C_SIM_RST | 81.00 | 12.00 | 79.78 | 82.22 | 11.49 | 12.51 |
| C_5V | 46.00 | 30.00 | 44.77 | 47.23 | 29.49 | 30.51 |
| C_2V8 | 72.00 | 50.00 | 70.78 | 73.22 | 49.49 | 50.51 |
| C_SNUB3 | -70.00 | -31.00 | -76.25 | -63.75 | -33.75 | -28.25 |
| D2 | -14.00 | -4.00 | -20.18 | -7.82 | -5.35 | -2.65 |
| C_IN | 24.00 | 50.00 | 22.77 | 25.23 | 49.49 | 50.51 |
| R_OPTO1 | -14.00 | -50.00 | -15.22 | -12.78 | -50.52 | -49.48 |
| R_SNUB2 | -70.00 | -9.00 | -72.03 | -67.97 | -9.91 | -8.09 |
| D_CLAMP_I | 37.00 | -11.60 | 35.85 | 38.15 | -13.80 | -9.40 |
| R_BASE2 | -12.00 | 2.00 | -13.37 | -10.63 | -2.61 | 6.61 |
| C_OSC1 | 50.00 | -5.00 | 48.77 | 51.23 | -5.51 | -4.49 |
| C_VDD3 | 62.00 | 9.00 | 60.77 | 63.23 | 8.49 | 9.51 |
| R_FB_BOT | 70.00 | -31.00 | 69.47 | 70.53 | -32.23 | -29.77 |
| R_PULL1 | 24.00 | -48.73 | 23.48 | 24.52 | -49.95 | -47.50 |
| C_3V3_IN | 69.00 | -36.00 | 67.78 | 70.22 | -36.51 | -35.49 |
| K1 | -40.00 | 38.00 | -62.01 | -17.99 | 28.75 | 47.25 |
| J_S1 | -84.00 | -35.00 | -88.78 | -79.22 | -40.33 | -29.67 |
| C_4V | 57.00 | 51.00 | 56.49 | 57.51 | 49.77 | 52.23 |
| U_OPTO2 | 7.50 | -50.00 | 2.69 | 12.31 | -52.53 | -47.47 |
| Q3 | -14.00 | -33.00 | -17.44 | -10.56 | -34.99 | -31.01 |
| U_MCU | 62.00 | 0.00 | 56.85 | 67.15 | -5.15 | 5.15 |
| L1 | 48.00 | 44.00 | 42.60 | 53.40 | 39.98 | 48.02 |
| C_VDDA | 56.00 | -13.00 | 54.77 | 57.23 | -13.51 | -12.49 |
| D3 | -14.00 | -42.00 | -20.18 | -7.82 | -43.35 | -40.65 |
| Q2 | -14.00 | 5.00 | -17.44 | -10.56 | 3.01 | 6.99 |
| R_PWRKEY | 65.00 | 14.00 | 64.47 | 65.53 | 12.78 | 15.22 |
| T1 | -40.00 | 19.00 | -48.37 | -31.63 | 9.38 | 28.62 |
| C_SNUB2 | -70.00 | 7.00 | -76.25 | -63.75 | 4.25 | 9.75 |
| R_SC2 | 22.47 | -34.52 | 21.24 | 23.70 | -35.05 | -34.00 |
| J_SIM | 80.40 | 4.00 | 71.97 | 88.84 | -3.05 | 11.05 |
| J_STAR | -84.00 | 28.00 | -88.78 | -79.22 | 22.67 | 33.33 |
| U_CS | 7.50 | -22.00 | 3.80 | 11.20 | -24.70 | -19.30 |
| U_4V | 37.00 | 43.00 | 34.12 | 39.88 | 39.52 | 46.48 |
| C_OSC2 | 50.00 | -11.00 | 48.77 | 51.23 | -11.51 | -10.49 |
| C_VDD2 | 70.00 | 0.00 | 68.78 | 71.22 | -0.51 | 0.51 |
| C_SIM_DATA | 86.00 | 16.00 | 84.78 | 87.22 | 15.49 | 16.51 |
| K3 | -40.00 | -38.00 | -62.01 | -17.99 | -47.25 | -28.75 |
| Y1 | 54.00 | -8.00 | 47.40 | 60.60 | -10.55 | -5.45 |
| C_SIM_VDD | 78.00 | 14.00 | 76.78 | 79.22 | 13.49 | 14.51 |
| FB_VDDA | 56.00 | -10.00 | 54.50 | 57.50 | -10.75 | -9.25 |
| C_1V8 | 68.00 | 50.00 | 66.78 | 69.22 | 49.49 | 50.51 |
| J_MAIN | -84.00 | 40.00 | -88.78 | -79.22 | 34.67 | 45.33 |
| C_VDDA_HF | 62.00 | -13.00 | 60.77 | 63.23 | -13.51 | -12.49 |
| R_OPTO2 | -14.00 | -54.00 | -15.22 | -12.78 | -54.52 | -53.48 |
| C_5V_IN | 42.00 | -47.00 | 40.77 | 43.23 | -47.51 | -46.49 |
| C_VCC4 | 69.00 | 53.00 | 67.78 | 70.22 | 52.49 | 53.51 |
| C_4V_HF | 70.00 | -15.00 | 68.78 | 71.22 | -15.51 | -14.49 |
| D_TVS | 19.00 | 50.00 | 15.38 | 22.62 | 48.09 | 51.91 |
| R_VS2 | 84.00 | 18.00 | 83.47 | 84.53 | 16.77 | 19.23 |
| R_STATUS | 70.00 | -18.00 | 69.47 | 70.53 | -19.23 | -16.77 |
| J_CS_IN | -83.40 | -22.00 | -89.40 | -77.40 | -33.16 | -10.84 |
| C_NRST | 70.00 | 8.00 | 69.49 | 70.51 | 6.78 | 9.22 |
| C_BOOT | 36.00 | 37.00 | 35.49 | 36.51 | 35.77 | 38.23 |
| J_VS_IN | -84.00 | -9.00 | -88.78 | -79.22 | -14.33 | -3.67 |
| Q_PWR | 61.00 | 17.00 | 59.01 | 62.99 | 13.56 | 20.44 |
| U_LTE | 75.60 | 35.00 | 61.30 | 89.90 | 21.00 | 49.00 |
| J_SWD | 87.20 | -16.00 | 85.40 | 89.00 | -22.88 | -9.12 |
| U_5V | 37.63 | 29.70 | 33.48 | 41.78 | 26.29 | 33.11 |
| R_PULL2 | 12.00 | -54.18 | 11.47 | 12.53 | -55.41 | -52.95 |
| MOV1 | -70.00 | 35.00 | -77.00 | -63.00 | 31.50 | 38.50 |
| C_4V_BULK | 69.00 | 44.00 | 68.49 | 69.51 | 42.77 | 45.23 |
Courtyard / Bounding Box Overlap Pairs
These are AABB footprint/courtyard overlaps from the bounds table. Copper DRC is clean, so this list should be treated as a mechanical/placement review list rather than a copper-short list.
Table
| Pair | X overlap | Y overlap |
|---|---|---|
| R_BASE3 - Q3 | 2.74 | 2.60 |
| R_BASE3 - D3 | 2.74 | 0.96 |
| K2 - D2 | 2.19 | 2.70 |
| D1 - R_BASE1 | 2.74 | 2.70 |
| D1 - K1 | 2.19 | 2.70 |
| L_EMI - U_LTE | 2.47 | 0.97 |
| C_VDD1 - Y1 | 2.45 | 1.02 |
| R_PWRKEY_PU - U_LTE | 1.05 | 0.23 |
| R_BASE2 - Q2 | 2.74 | 3.60 |
| C_OSC1 - Y1 | 2.45 | 0.06 |
| J_S1 - J_CS_IN | 9.55 | 3.49 |
| D3 - K3 | 2.19 | 2.70 |
| C_OSC2 - Y1 | 2.45 | 0.06 |
| Y1 - FB_VDDA | 3.00 | 1.30 |
| J_CS_IN - J_VS_IN | 9.55 | 3.49 |
| U_LTE - C_4V_BULK | 1.02 | 2.45 |
Total overlap pairs: 16.
Notes
- Some overlap pairs are likely intentional or benign because the layout inspection reports coarse footprint/courtyard bounding boxes, not actual 3D model collision volumes.
- Through-hole and large-outline parts should still be reviewed visually in 3D/Gerber preview before manufacturing.
- The right edge now satisfies the requested board-edge bound from the returned layout aggregate: max X = +89.90 mm. This gives approximately 0.10 mm to the board edge, not a full 1.00 mm. The limiting part is U_LTE, whose current footprint bound reaches X = +89.90 mm. Moving U_LTE farther left would be needed for a full 1 mm margin on every footprint, but I did not move it because that would alter the RF/LTE block placement more substantially.
Summary
Component Bounds Table
Courtyard / Bounding Box Overlap Pairs
Notes
