Audio Processor PCB Design


  • Connected J1:V-BUS, J1:V-BUS__1, L1:P1, U5:IN, U2:5V, U4:VDD, U4:HPVDD
  • Connected U5:OUT, L2:P1, U2:3V3, U2:3V3_1, U1:IOVDD, U1:DVDD
  • Connected U6:OUT, L3:P1, U1:PVDD, U1:AVDD
  • Connected U2:SDIO-DATA2_GPIO22_SDA_D4, U3:SDA, U1:SDA/COUT, R1:P2
  • Connected U2:SDIO-DATA3_GPIO23_SCL_D5, U3:SCL, U1:SCL/CCLK, R2:P2
  • Connected Y1:3 to U1:MCLKI
  • Connected U1:SCL/CCLK, U2:D8_SCK_GPIO19_SDIO-CLK, J4:1
  • Connected U1:CLATCH/WP, U2:D7_RX_GPIO17, J4:2
  • Connected U1:SDA/COUT, U2:D9_MISO_GPIO20_SDIO-DATA0, J4:3
  • Connected J1:S to C2:P1
  • Connected C2:P2 to U1:ADC0
  • Connected J1:R to C3:P1
  • Connected C3:P2 to U1:ADC1
  • Connected U1:VOUT0 to R3:P1
  • Connected R3:P2 to U4:INL+
  • Connected U1:VOUT1 to R4:P1
  • Connected R4:P2 to U4:INR+
  • Connected U4:OUTL to J3:1
  • Connected U4:OUTR to J3:2
  • Connected J1:CC1 to R5:P1
  • Connected J1:CC2 to R6:P1
  • Connected J1:GND, J1:GND__1, J1:SHIELD, J1:SHIELD__1, J1:SHIELD__2, J1:SHIELD__3, U1:AGND, U1:DGND, U1:PGND, U4:PGND, U4:SGND, U2:GND, U2:GND_1, U2:GND_PAD, U3:GND, U5:GND, U6:GND, D1:G, D1:G, D2:G

Worked

Work completed
  • Steps 1–6 of the implementation plan (project description, system architecture, ICs, active/passive parts, connectors/peripherals) have been finished.
Tasks remaining
7. Make all net connections
8. Review schematic for completeness
9. Footprint review
10. Define 2-layer PCB stackup
11. Set board size to 50 mm × 35 mm
12. Assign copper layers for VCC and GND planes
13. Enable ground fills on both layers
14. Add four M2 mounting holes (3 mm from edges)
15. Pause for review of dimensions, mounting holes, and stackup
Success criteria have not yet been met; the netlist and layout preparation are still pending.
Recommended next step
Proceed with step 7: wire up all power, signal, and ground nets in the schematic.

Flux stopped


U6
D1
U2
U1
D2

FrontRow prototype 01

FrontRow prototype 01 thumbnail