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⚡ EMC DRC
WIP / NOT YET STARTED
Surface coupling paths, not just bad traces.
Goals
- Give Flux users and our agent early, actionable EMI/EMC feedback at the PCB layout stage - before prototypes and chamber time
- Implement a focused set of geometry- and topology-driven checks that are explainable, parameterized, and portable across CAD inputs
- Make Flux the first cloud-native EDA tool with built-in EMC design rule checking that doesn't require a separate licensed tool
Team
Actively building
- TBD: engineering DRI
- EE domain, rule selection & prioritization
- TBD: UX design
Supporting roles
- TBD
- TBD
Scope management [read this first]
- [current step] Define the V1 rule set, schema requirements (
InterferencePotential/Isolation), and data dependencies. - [next step] Build the geometry/topology DRC engine (spatial index, net graph, plane intersection) and implement P0 checks.
- [later step] Implement P1 checks (crosstalk, SMPS hot-loop, diff pair) and reporting UX.
- [last step] Ship V1. Evaluate adding solver-based checks (plane resonance, far-field estimation) as optional analysis modules.
User-facing problem
- EMC failures are discovered too late. Most engineers find EMI problems during prototype testing or compliance chamber visits - the most expensive possible time to discover a return-path discontinuity or a missing filter.
- Existing EMC DRC tools are expensive, siloed, and hard to integrate. EMIStream costs a separate license and only works via ODB++ export or Altium extension. HyperLynx DRC is locked into Siemens flows. There is no accessible, cloud-native option.
- KiCad and other open-source tools don't cover EMC. KiCad's DRC is strong for manufacturability and connectivity but does not natively encode return-current continuity, slot/plane resonance, or common-mode launch concepts.
- Our AI agent has no EMC awareness. When the agent routes or places components, it has no signal about whether it's creating a return-path discontinuity, routing near a plane edge, or placing a decap too far from an IC power pin.
TL;DR: there is no fast, integrated, explainable EMC feedback loop in any cloud-native EDA tool, and our users and agent are flying blind on the issues that cause the most painful board respins.
Engineering problems
- Many EMC checks require topology awareness (return current inference, port/connector semantics, power-stage loop identification) that goes beyond "constraint between two geometric primitives"
- We need a normalized PCB model with layers, nets, zones, components, vias, and stackup - and the ability to ingest it from our native format as well as ODB++ and IPC-2581
- Return-path and plane-intersection checks require robust polygon operations (plane split detection, void intersection, corridor overlap)
- Some checks depend on stackup knowledge (reference adjacency, via stub length) which may not always be specified - we need a two-tier system (stackup-independent vs. stackup-dependent checks)
- We need a schema extension (
InterferencePotentialandIsolation) to let users and the agent tag nets with aggressor/victim roles, edge rate classes, port relevance, and isolation presets
Proposed solution
Core architecture
- Spatial index (R-tree) for geometry queries - distance to plane edge, keepout violations, via spacing
- Net graph (segments/vias as edges/nodes) for path-based checks - length, via count, layer transitions, current loop proxies
- Plane intersection engine for return-path rules - intersect trace corridors with plane polygons/voids
- All thresholds parameterized and tied to Isolation presets, following EMIStream's "Expert option" pattern
V1 rule set (16 checks, prioritized)
P0 - ship first (6 checks)
Table
| Check | What it catches | Effort |
|---|---|---|
| Signal over plane split/void | Return-path discontinuity - the single most common catastrophic EMC mistake | Medium |
| Reference change without stitching | Loop-area growth and mode conversion at layer transitions | Medium |
| Traces near plane edge | Edge fields fringe outward -> efficient radiator | Low |
| Plane-outline stitching density | Missing stitch vias along plane edges create slot antennas | Low-Medium |
| Decap connection geometry | Traces between decap pads and vias, excessive pad-to-via distance, shared vias | Medium |
| Filter/protection placement at connector boundary | Missing or distant filters on connector nets - classic common-mode launch | Medium-High |
P1 - ship second (7 checks)
Table
| Check | What it catches | Effort |
|---|---|---|
| Net length + via count risk scoring | Long traces act as antennas; excessive vias add discontinuities | Low |
| Crosstalk risk (aggressor/victim) | Parallel coupling between fast aggressors and sensitive victims | Medium |
| Diff pair skew + symmetry near connectors | Imbalance -> differential-to-common-mode conversion -> radiation | Medium |
| Switch-node keepout and overlap | Uncontained high dv/dt copper couples into victims | Medium-High |
| Hot-loop area proxy | SMPS hot loop perimeter/area too large -> radiation | High |
| Feedback routing near SW/inductor | Feedback net picks up switching noise - common SMPS failure mode | Medium |
| SG guard/via-fence checks | Broken or sparse guard traces on sensitive/ESD zones | Medium |
P2 - later (3 checks)
Table
| Check | What it catches | Effort |
|---|---|---|
| IC ground split / neck-down detection | Return discontinuities directly under ICs | Medium-High |
| PDN plane resonance "needs analysis" flag | Large planes with sparse decaps likely to resonate | Low (flag) / High (solver) |
| Via stub length flag | Through-vias with stubs above threshold at high speeds | Medium |
Schema extension
InterferencePotential (per-net metadata)
role:AGGRESSOR|VICTIM|BOTH|NEUTRALcouplingModes: set ofCAPACITIVE_E,INDUCTIVE_H,COMMON_IMPEDANCE,SUPPLY_INJECTION,MODE_CONVERSION_PORTedgeRateClass:SLOW|MODERATE|FAST|ULTRAFASTportRelevance:NONE|INTERNAL|CONNECTOR_NET|CABLE_SHIELD|CHASSIS_BONDreferenceNeed:CONTINUOUS_REQUIRED|PREFERRED|DONT_CARE
Isolation (design-intent zones)
preset:NONE|CONNECTOR_BOUNDARY|HOT_LOOP_CONTAINMENT|QUIET_ANALOG|NOISE_ENCAPSULATION|ANTENNAkeepouts: polygons + layer masksspacing: per-class distanceslayerPolicy: allowed layers + required adjacenciesstitchingPolicy: via types + max spacing
Stackup handling
- Tier A (stackup-independent): plane-edge distance, filter placement, decap pad-to-via distance, via fence spacing, net length/via count, crosstalk adjacency
- Tier B (stackup-dependent): via stub length, reference adjacency, full return continuity, plane resonance flags
- If stackup is unspecified, run Tier A and prompt the user to provide stackup info to unlock Tier B
Reporting
Every violation includes:
- Why it matters - the EMC consequence in plain language
- How it couples - the physical coupling mechanism (return path, edge radiation, common impedance, etc.)
- Suggested fix(es) - one or two concrete actions (reroute, add stitching via, move filter, shrink SW copper)
Opportunities this unlocks
- AI-native EMC workflow - the agent can check its own work as it routes and places, catching return-path breaks and decap issues before the user ever sees them
- "EMC confidence score" per board - a visible, explainable metric that builds trust and differentiates Flux from tools that treat EMC as an afterthought
- Competitive moat - no other cloud-native EDA tool offers built-in EMC DRC; EMIStream requires a separate license and ODB++ export, HyperLynx is Siemens-only
- Upsell path to analysis modules - V1 DRC creates demand for optional plane resonance analysis and far-field estimation as premium features
Open questions
- Net classification bootstrapping: most of these checks only work well if nets are tagged with roles, edge rates, and port relevance - how much can we infer automatically vs. requiring user input?
- The agent should be able to auto-tag based on component datasheets and schematic connectivity, but we need a confidence model
- Polygon engine robustness: return-path checks live or die by plane intersection quality - we need to evaluate whether our existing geometry stack can handle void/split detection at production speed
- False positive management: EMC rules are inherently heuristic - we need to make it trivial to suppress individual violations and adjust thresholds per-project
- Connector semantics: several high-value checks (filter placement, ESD protection, boundary containment) require knowing which footprints are connectors - we don't have this metadata consistently today
- SMPS identification: hot-loop and switch-node checks require identifying SMPS topologies - this is a non-trivial classification problem if not user-tagged
Competitive landscape
EMIStream (NEC / DEMITASNX)
The closest comparable product. 15 curated EMI rule checks distilled from 150+ investigated rules, plus optional SMPS (9 rules) and ESD (10 rules) add-ons. Includes PEEC-based plane resonance analysis and far-field estimation from plane-edge voltage. Excel reporting with error locations and corrective advice.
- Key differentiator: curated defaults, AI-driven error screening, batch execution
- Limitation: requires separate license, ODB++ export, no cloud-native workflow. Business transitioning to Microwave Factory Co. (April 2026)
Siemens HyperLynx DRC
Electrical DRC focused on reference/return path integrity and topology checks. Uses a 3D geometry engine. Marketed as a complement to simulation - removes issues before deeper analysis.
- Limitation: locked into Siemens PCB flows
Cadence Sigrity / Allegro
Full-wave SI/PI analysis; addresses SSN, coupling, decap issues. Constraint Manager supports DRC workflows. In-design return-path analysis available.
- Limitation: enterprise pricing, not a standalone EMC rule checker
Ansys SIwave
PI/SI/EMI analysis for PCBs/packages. Plane resonance is a core concept. Strong for resonance and near/far-field workflows.
- Limitation: solver-heavy, not a fast DRC pass
Zuken CR-8000 (Design Force PI/EMI Advance)
PCB-level EMI and power supply system analysis including worst-case emissions with cables and heatsinks. Integrated in CR-8000 environment.
- Limitation: not standalone, CR-8000 ecosystem only
Build vs. buy guidance
- Build: geometry/topology DRC checks grounded in public-domain physics and published guidelines (LearnEMC, vendor app notes, academic papers). All V1 checks are implementable from first principles.
- Buy/partner: heavy solvers (plane resonance PEEC, 3D EM) and compliance test integration - where commercial tools have validated engines. Consider as P2/P3 add-on modules.
- Do not clone: implement rules based on physics, not copied thresholds or proprietary heuristics from EMIStream or others.
Reference material
- LearnEMC - PCB Layout - canonical framing of sources, victims, coupling paths
- LearnEMC - Identifying Current Paths
- LearnEMC - Decoupling
- EMIStream Product Page
- Initial rule research table (Smartphone Hardware Features)
Goals
Team
Actively building
Supporting roles
Scope management [read this first]
User-facing problem
Engineering problems
Proposed solution
Core architecture
V1 rule set (16 checks, prioritized)
Schema extension
Stackup handling
Reporting
Opportunities this unlocks
Open questions
Competitive landscape
EMIStream (NEC / DEMITASNX)
Siemens HyperLynx DRC
Cadence Sigrity / Allegro
Ansys SIwave
Zuken CR-8000 (Design Force PI/EMI Advance)
Build vs. buy guidance
Reference material
![PICO Smart Automation Controller [Prod_V1_AUTO_NET_CLASS_12-10] mPfB thumbnail](https://img-cdn.flux.ai/eyJidWNrZXQiOiJncmF2aXRvbi1lbGVjdHJpYy1zeW1ib2xzIiwia2V5IjoiZG9jdW1lbnRfYXNzZXRzL1BJQ08tU21hcnQtQXV0b21hdGlvbi1Db250cm9sbGVyLWltYWdlLTUwNzcyZWQ5LTZiOTctNGE5Yi04MTI1LTkyMGFhYjk4Mjc1OS5wbmciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjEzNiwiaGVpZ2h0IjoxMzYsImZpdCI6ImNvbnRhaW4iLCJiYWNrZ3JvdW5kIjp7InIiOjAsImciOjAsImIiOjAsImFscGhhIjowfX19LCJvdXRwdXRGb3JtYXQiOiJ3ZWJwIn0=)