Nixie Tube Decade Counter Setup
1:21
Planning circuit steps.
Defining pinout for connections.
Adding debounced components.
Integrating debounce components.
Planning debouncing and reset.
Goal acknowledged: integrate a 5 V 555‑clocked CD4017 with AUTO/STEP, RESET, and a 2×6 outputs header.
Plan:
- Clock: Keep IC1 with R4/TC; add 100 nF decouplers at IC1/U2/U3.
- Conditioning + select: Route IC1:Q through U2 to U3 CLK; optional 100 Ω series; add Pin Header 01x03 2.54mm AUTO/STEP with center to CLK.
- STEP: Add debounced pushbutton via spare U2 gate to STEP side of selector; use 10kΩ Resistor + 100nF Capacitor.
- RESET: Add pull network per CD4017 datasheet and Pin Header 01x02 2.54mm to U3 RESET.
- Outputs: Place Pin Header 02x06 2.54mm for Q0–Q9 plus GND and VCC.
Click Start on the plan bar to run this.
Plan
- Design a 555‑clocked decade counter for a Nixie countdown circuit operating at 5 V, integrating a CD4017 decade counter with an AUTO/STEP selectable clock source, RESET input, and a 2×6 output header for displaying the counter outputs.
#Implementation plan
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Clock Source and Decoupling
- Confirm the NE555 (IC1) is configured as an astable clock using the existing trimpot (R4: 3296Y-1-503LF) and timing capacitor (TC).
- Add 100 nF decoupling capacitors at the power pins of NE555 (IC1), 74HC14 (U2), and CD4017 (U3) to ensure power supply stability.
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Clock Conditioning and AUTO/STEP Selection
- Buffer the NE555 output (IC1:Q) through one gate of the 74HC14 (U2) to clean up the clock signal.
- Add an optional 100 Ω series resistor at the output of the 74HC14 if needed for signal conditioning.
- Integrate a 3‑pin AUTO/STEP header. Wire the center pin to the clock input of the CD4017 (U3) and allow selection between the auto clock (from the NE555 via U2) and a manual step signal.
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Manual STEP Input
- Add a debounced pushbutton by routing its signal through another unused gate in the 74HC14 (U2).
- Connect the output from the debounced pushbutton to the STEP side of the AUTO/STEP selector header, ensuring that a clean pulse is generated when pressed.
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RESET Input
- Implement the pull network as recommended in the CD4017 datasheet for the RESET function.
- Add a 2‑pin RESET header and connect it to the RESET pin of the CD4017 (U3) along with the pull network.
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Output Header Integration
- Place a 2×6 header on the PCB for the outputs (Q0–Q9) of the CD4017 (U3), ensuring that GND and VCC are also accessible on this header.
- Label the header clearly to indicate the connection of Q0-Q9, GND, and VCC.
#Success criteria
- The NE555, 74HC14, and CD4017 are correctly configured and connected to form a stable clock and counter circuit.
- The AUTO/STEP header successfully allows selection between an automatic clock and a manual step input.
- The RESET input is functioning correctly with the configured pull network.
- The 2×6 output header correctly displays outputs Q0–Q9 along with power pins, and all components operate at a 5 V logic level.
Choose output header pinout
Find 2x6 header part
Debounce values decision
Reset behavior choice
Clock range target
111 days
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