Smart Relay Logic Board Design

Updated 4 layout rules

0:03

Set Layout's minTraceWidth to "0.20mm"

Set Layout's traceWidth to "0.25mm"

Set Layout's keepOut to "0.20mm"

Set Layout's boardInsetMargin to "0.25mm"

4 days

flux

0:00

Work done
  • Reviewed the current schematic and layout state for U1, U2, P1, P2, passives, test points, and mounting holes.
  • Confirmed the actual blocker in the layout: the board still contains many legacy route segments on invalid inner layers from an older 4-layer state, plus overlapping and floating copper.
  • Reapplied conservative board-level layout rules for the current 2-layer board and removed one stale layout-level layer override.
  • Verified that manufacturing MPN and footprint checks are clean, but PCB DRC is still not clean.
Success criteria review
  • ✅ Identified the root cause of the remaining PCB issues.
  • ✅ Verified the project is using a 2-layer stackup in the active layout view.
  • ❌ Component placement was not completed in this session.
  • ❌ Airwires, floating copper, and overlapping copper were not cleared.
  • ❌ The antenna keepout and final silkscreen placement were not completed.
Next steps The next step is to remove or regenerate the legacy invalid-layer route segments, then place U1 at the board edge with antenna clearance, place the remaining components per the placement plan, and re-run DRC until airwires and copper errors are resolved. I cannot continue that execution in this session.
4 days
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Design Notes
Scope
Production-grade 2-layer SELV logic board for an ESP8266 smart relay controller.
Locked requirements
  • MCU module: ESP-12F
  • Input rail: 5 V SELV
  • Local regulation: MCP1700-3302E, 5 V to 3.3 V
  • Board size: 55 mm x 45 mm
  • Layer count: 2
  • Placement: all components on top side
  • Bottom copper: solid ground pour
  • RF: ESP-12F antenna keepout required
  • Mechanical: 4 x M3 mounting holes
  • User access: exact 2x7 connector pinout, 4-pin programming header, GPIO0 flash test point
  • Indicators: active-low status LED on GPIO2
  • Validation: test points on power rails and used GPIOs
  • Marking: silkscreen labels for connectors, test points, and board/version ID
Safety intent
  • Logic board remains SELV only.
  • No mains or hazardous voltages are routed on this board.
  • External interfacing should remain within SELV limits.
Design defaults selected
  • Use 10 kOhm bootstrap pulls for ESP8266 boot-critical pins.
  • Use 100 nF local decoupling near ESP module supply pins.
  • Use 10 uF bulk capacitance on 5 V input and 3.3 V rail.
  • Use UART header exposing 3.3 V, GND, TXD0, RXD0.
  • Place the ESP-12F at a board edge with copper exclusion under the antenna zone.

    Scope

    Locked requirements

    Safety intent

    Design defaults selected

Documents

    design-notes

    Project Specification

Assets

Assets are files uploaded to this project which can be used in various ways.

ZAPP-LB-V1 Smart Relay Logic Board thumbnail
2-layer SELV ESP8266 smart relay logic board using an ESP-12F module, MCP1700-3302E 5V-to-3.3V LDO, exact 2x7 relay/control connector pinout, 4-pin UART programming header, GPIO0 flash test point, active-low GPIO2 status LED, power and GPIO test points, 55x45 mm board outline, top-side assembly, bottom solid ground pour, ESP-12F antenna keepout, 4 M3 mounting holes, and silkscreen connector labels for production use.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$2.67–$247.95

Digi-Key

$2.76–$707.06

LCSC

$6.26–$81.33

Mouser

$4.59–$486.15

TME

$0.84

Verical

$2.53–$75.21

Controls