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Capture design constraints
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Compact LTM4712 Relayout Design Notes
Source Circuit
- Target reference: Analog Devices EVAL-LTM4712-A2Z.
- Function: 5 V to 36 V input, 12 V nominal output, quad PolyPhase LTM4712 buck-boost regulator.
- Same-spec current target from the user guide: 48 A max in buck / buck-boost operation for VIN = 10 V to 36 V; 24 A max in boost operation for VIN = 5 V to 10 V.
- Default switching frequency: 400 kHz.
- Test points and demo-board-only banana jacks / jumper hardware are intentionally omitted for compact form factor.
Implemented Schematic So Far
- Added 4x LTM4712EY#PBF modules, VIN/VOUT/GND high-current connector placeholders, the eval-board capacitor banks, frequency resistors, RUN divider, soft-start capacitors, feedback resistor, optional trim resistor, and 2 mΩ phase shunts.
- Added a primary feedback resistor footprint RFB: 2.26 kΩ for 12 V; replace with 2.08 kΩ for 13 V.
- Added optional parallel trim footprint RTRIM: DNP by default; populate about 27 kΩ in parallel with 2.26 kΩ to shift close to 13 V.
Feedback Resistor for 12 V to 13 V
The LTM4712 has an internal 100 kΩ feedback resistor from VOUT to FB. For N paralleled modules with all FB pins tied together, the effective top feedback resistance is 100 kΩ / N, so:
RFB = 100 kΩ / (N x (VOUT - 1 V))
For N = 4:
- 12.0 V target: RFB = 100 kΩ / (4 x 11) = 2.273 kΩ. The eval board uses 2.26 kΩ (R12), which is the selected 1% value.
- 13.0 V target: RFB = 100 kΩ / (4 x 12) = 2.083 kΩ. Use 2.08 kΩ 1% as the easy-change resistor value.
Validation Status
- ERC was run after initial wiring. It still reports floating-pin warnings, mainly because the LTM4712 BGA has many duplicate GND/SGND and intentional unused SW/monitor/clock pins that need a final cleanup pass.
- U3 GND/SGND duplicate pins were partially remediated after the first ERC run.
- The schematic is not yet ready to advance to layout/routing until remaining ERC warnings are cleared or intentionally marked no-connect where allowed by the datasheet.
Compact Layout Constraints
- Use at least a 4-layer board: top power components/signals, inner GND plane, inner power plane/current spreading, bottom power/signal.
- Place the four LTM4712 modules close together and symmetrically for current sharing and thermal balance.
- Use very wide VIN/VOUT copper pours and multiple thermal/current vias; do not use vias-in-pad unless capped/filled.
- Place high-frequency ceramic input capacitors tight to VIN/GND balls and output ceramics tight to VOUT/GND balls.
- Keep FB/FREQ/SS/COMP/SGND components on a quiet SGND island, tied to power GND under the modules at the recommended point.
- High-current input/output connectors or pads must be sized for 48 A continuous with copper/thermal validation.
Source Circuit
Implemented Schematic So Far
Feedback Resistor for 12 V to 13 V
Validation Status
Compact Layout Constraints
