Power Design for IoT Device

flux

2:46

Consulting on component suitability.

Verifying USBLC6-2SC6Y details.

Examining USBLC6-2SC6Y specifications.

Linking components for clarity.

Accessing knowledge base.

Looking for "device description, number of protected lines, and application (USB 2.0/USB-C)" in en.DM00055262.pdf

Looking for "IEC 61000-4-2 ESD robustness (contact and air discharge) values" in en.DM00055262.pdf

Looking for "line capacitance (per IO line) and capacitance to ground" in en.DM00055262.pdf

Looking for "reverse standoff voltage (VRM) and breakdown voltage (VBR) for VBUS pin" in en.DM00055262.pdf

Looking for "clamping voltage at specified peak pulse current for VBUS and IO lines" in en.DM00055262.pdf

Looking for "recommended application schematic and pinout, which pin is VBUS and GND" in en.DM00055262.pdf

Gathering ESD protection information.

Ya, bisa. Di proyek ini D3 memang sudah memakai USBLC6-2SC6Y dan cocok untuk port USB‑C charge‑only J3 sebagai proteksi ESD/TVS, khususnya pada VBUS.
Ringkasan data penting dari datasheet USBLC6-2SC6Y:
  • Aplikasi: proteksi ESD untuk antarmuka kecepatan tinggi (USB 2.0 hingga 480 Mb/s). Melindungi 2 jalur data.
  • Level ESD (IEC 61000-4-2): ±8 kV contact, ±15 kV air.
  • Kanal VBUS:
    • Reverse standoff (dirating) diuji pada 5.25 V (leakage 10–150 nA).
    • Breakdown VBR (VBUS–GND) 6 V (IR = 1 mA).
    • Clamping VCL: 12 V @ 1 A (8/20 µs), 17 V @ 5 A (8/20 µs).
  • Kapasitansi:
    • I/O–GND: 2.5–3.5 pF (VR = 1.65 V).
    • I/O–I/O: 1.2–1.7 pF (VR = 1.65 V).
  • Pinout: I/O1, I/O2, GND, VBUS.
Catatan penerapan pada desain Anda:
  • VBUS: Penempatan D3 di jalur VBUS J3 → U4 sudah tepat. VBR 6 V berada di atas rentang 5.25 V, sehingga tidak mudah “false trigger” saat 5 V normal, sesuai best practice.
  • CC lines: Untuk CC1/CC2, tetap pakai ESD kapasitansi sangat rendah seperti D1 dan D2. Best practice: proteksi ESD untuk jalur data/negosiasi memakai TVS bidirectional berkapasitansi di bawah 1 pF per line; pilihan Anda di CC sudah tepat.
  • Penempatan: Pasang komponen proteksi sedekat mungkin ke konektor J3, jalur ke GND sangat pendek dengan via langsung ke ground plane. Pertimbangkan juga elemen pembatas arus/EMI di sisi VBUS sesuai kebutuhan sistem.
Jika Anda ingin, saya bisa cek cepat koneksi pin D3 (VBUS dan GND sudah benar; I/O1/I/O2 boleh tidak dipakai bila tidak ada D+/D-) dan beri rekomendasi penataan layout di sekitar konektor USB‑C.
Minta cek koneksi D3
Tanya perlunya EMI filter
Tanya proteksi D+ D-
Tanya penempatan layout
Konfirmasi CC line protection
138 days
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    Updated ERC-Cleaned Design Without Q2, C1, and C2 (ERC-verified removal of Q2 2N7002K, C1 10uF bulk, and C2 100nF decoupling; no changes to remaining power paths or circuitry)

    Properties

    Diagram
    


  
    
  
  
    
  



""System Power Architecture""


""USB-C Charge-Only""













"J1 Battery Connector"
BAT rail
"U4 SLM6400 Charger"
"U1 A7670C-LASE LTE Module"
"U6 TPS62130 node_3V3 DC-DC"
3V3 rail
"J3 USB-C Connector"

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