PCB Layout Configuration
1:21
Analyzing the schematic.
Analyzing the PCB layout.
Applying design rules.
Considering routing constraints.
Adjusting component placement.
Running design review.
Analyzing the PCB layout.
Working.
Working.
Working.
Analyzing the PCB layout.
Working.
I’ve set the routing constraints you asked for.
Applied:
- Q1, D1, T1:
traceWidth = 1.0mmandminTraceWidth = 1.0mm - J1, J2, C3:
minKeepOut = 6.0mm
What this means:
- Your primary switching loop now carries a hard 1.0 mm routing constraint on the critical cluster, so when you route those airwires manually, Flux will enforce the wider copper on that section.
- The secondary/output section now has a 6.0 mm isolation buffer around J1/J2/C3 to help maintain physical separation from the primary side.
One limitation:
- I did not physically draw the copper traces. I was able to apply the DRC/layout constraints, but the primary loop still needs to be routed on the PCB canvas.
Current status:
- Airwires are still present, so the board is not routed yet. That matches the expected workflow after constraint setup. The recommended verification pattern is to apply exact-width rules first, then route, then re-check airwires/DRC.
Recommended manual routing order:
- Route +12V → T1 primary → Q1/D1 loop first, keeping it as short and compact as possible.
- Keep that loop entirely on Top Layer if possible.
- Do not route primary copper into the 6 mm keepout region around J1/J2/C3.
- After that, route the low-power NE555 section.
- Re-run DRC and check for remaining airwires.
Also, the rule syntax requires exact metric values like
1.0mm and 6.0mm, which is why I used those explicit numbers.If you want, I can next help you define:
- a clearance rule for the primary loop, or
- a step-by-step manual routing plan for the critical traces.
Define clearance rule
Manual routing steps
Check remaining issues
3 days
Updated 9 layout rules
Set Q1's traceWidth to "1.0mm"
Set Q1's minTraceWidth to "1.0mm"
Set D1's traceWidth to "1.0mm"
Set D1's minTraceWidth to "1.0mm"
Set T1's traceWidth to "1.0mm"
Set T1's minTraceWidth to "1.0mm"
Set J1's minKeepOut to "6.0mm"
Set J2's minKeepOut to "6.0mm"
Set C3's minKeepOut to "6.0mm"
3 days
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Project Specification
Architecture
Diagram
Scope
Create the NE555 astable timer core for a signal injector, add a low-side MOSFET switching stage, integrate a 1:1 RF isolation transformer primary between +12 V and the MOSFET drain, and expose the transformer secondary on external test leads with an intentional impedance imbalance.
Requirements
- Add a standard 8-pin NE555 timer IC.
- Connect VCC and RESET to a 12 V rail.
- Connect GND to ground.
- Tie Trigger and Threshold together.
- Add a 10 nF capacitor from Control Voltage to ground.
- Add an IRLZ44N N-channel MOSFET driven from the NE555 output.
- Add a 10 kOhm gate pull-down resistor to ground.
- Tie the MOSFET source to ground.
- Add a 1:1 RF isolation transformer.
- Connect one end of the transformer primary to +12 V.
- Connect the other end of the transformer primary to the MOSFET drain.
- Connect the top transformer secondary leg directly to an external Red Clip terminal.
- Connect the bottom transformer secondary leg to an external Black Clip terminal through a 100 nF series capacitor.
- Preserve the existing NE555 oscillator, MOSFET switch, and transformer primary drive circuitry without modification.
- Document that the 100 nF series capacitor intentionally creates output impedance imbalance to promote common-mode leakage current injection.
- Leave the circuit ready for later timing-network refinement and load-stage expansion.
PCB Layout Configuration
- Board outline set to a rectangular 100 mm x 80 mm industrial form factor.
- Stackup set to a custom 4-layer configuration for EMC-oriented routing.
- Layer 1 (Top Copper): component placement and standard routing.
- Layer 2 (Mid-Layer 1): solid ground reference plane.
- Layer 3 (Mid-Layer 2): dedicated 12 V power plane.
- Layer 4 (Bottom Copper): overflow routing and return path support.
- Board inset margin / universal keepout configured to 0.25 mm.
Design Summary
Status: Draft / Review / Approved
Manufacturing target: Prototype / EVT / DVT / PVT / Production
Software / firmware: repository link
Scope
Purpose
In scope
Out of scope
System context
Requirements
Functional
Electrical
Mechanical / environmental
Key constraints
Dependencies and risks
Dependencies
Key risks
Validation
Success criteria
Planned checks
Release-facing notes
Expected deliverables
Special release notes
Change notes / open questions
-Changes in this revision
- Added an IRLZ44N-family low-side MOSFET stage on the NE555 output.
- Added a dedicated 10 kOhm gate pull-down resistor to ensure a defined off state.
- Added a 1:1 RF isolation transformer primary between +12 V and the MOSFET drain.
- Added external Red Clip and Black Clip output terminals on the transformer secondary.
- Added a 100 nF series coupling capacitor on the bottom secondary leg to intentionally create output impedance imbalance for common-mode leakage current injection.
-Open questions
- The transformer primary is pulsed at about 33.1 kHz by the existing NE555 and MOSFET stage.
- Because the output is now intentionally imbalanced on the transformer secondary, the external interface should be treated as a signal injection output and handled with appropriate safety precautions during bench testing.
-Open questions
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