Diagram

• Add a standard 8-pin NE555 timer IC.
• Connect VCC and RESET to a 12 V rail.
• Connect GND to ground.
• Tie Trigger and Threshold together.
• Add a 10 nF capacitor from Control Voltage to ground.
• Add an IRLZ44N N-channel MOSFET driven from the NE555 output.
• Add a 10 kOhm gate pull-down resistor to ground.
• Tie the MOSFET source to ground.
• Add a 1:1 RF isolation transformer.
• Connect one end of the transformer primary to +12 V.
• Connect the other end of the transformer primary to the MOSFET drain.
• Connect the top transformer secondary leg directly to an external Red Clip terminal.
• Connect the bottom transformer secondary leg to an external Black Clip terminal through a 100 nF series capacitor.
• Preserve the existing NE555 oscillator, MOSFET switch, and transformer primary drive circuitry without modification.
• Document that the 100 nF series capacitor intentionally creates output impedance imbalance to promote common-mode leakage current injection.
• Leave the circuit ready for later timing-network refinement and load-stage expansion.

• Added an IRLZ44N-family low-side MOSFET stage on the NE555 output.
• Added a dedicated 10 kOhm gate pull-down resistor to ensure a defined off state.
• Added a 1:1 RF isolation transformer primary between +12 V and the MOSFET drain.
• Added external Red Clip and Black Clip output terminals on the transformer secondary.
• Added a 100 nF series coupling capacitor on the bottom secondary leg to intentionally create output impedance imbalance for common-mode leakage current injection.

• The transformer primary is pulsed at about 33.1 kHz by the existing NE555 and MOSFET stage.
• Because the output is now intentionally imbalanced on the transformer secondary, the external interface should be treated as a signal injection output and handled with appropriate safety precautions during bench testing.