PCB Design for Cat Deterrent
Worked
I’m blocked again because there are no available ACUs, so I can’t continue routing or run more checks.
What I completed this session:
- Reduced airwires from 33 to 20 at the last check.
- Routed more
VBUS_5V,3V3_LOGIC,PUMP_GATE,PIR_OUT,LED_STAT, and MOSI-related connections. - Removed DRC-reported overlapping copper fragments so the board is not left with known shorting trace pieces.
What remains:
- Finish blocked dense nets:
RESET,PB1/MISO,PB2/SCK, LED anode, some 3.3 V/passive branches, and ground. - Re-run DRC/airwire checks.
- Likely adjust placement slightly around the ISP/ATtiny/passive cluster if those routes remain blocked.
Finish up quickly fast as you can no delay
Worked
I’m blocked: there are no available ACUs, so I can’t execute more routing or cleanup right now.
What I completed:
- Rechecked the current layout/routing state.
- Tried direct routing on the tight ATtiny85 ↔ ISP area.
- Re-ran placement optimization to open routing space around J4/ISP, U1, reset parts, and nearby passives.
- Final check after that showed the board is still not complete: 28 airwires, 12 dangling trace warnings, and 8 overlapping-copper errors remain.
What remains:
- Delete or repair the overlapping copper first.
- Finish routing the dense ISP/reset/pot/keep-alive nets.
- Finish ground and remaining 3.3 V / 5 V branches.
- Run final airwire/DRC checks before manufacturing export.
The layout is not ready for fabrication yet; once ACUs are available, the fastest path is copper cleanup first, then finish the remaining routes.
Locate copper errors
List remaining airwires
Fast routing order
Check placement nudges
