PCB Design for Cat Deterrent
Worked
I’m blocked again because there are no available ACUs, so I can’t continue routing or run more checks.
What I completed this session:
- Reduced airwires from 33 to 20 at the last check.
- Routed more
VBUS_5V,3V3_LOGIC,PUMP_GATE,PIR_OUT,LED_STAT, and MOSI-related connections. - Removed DRC-reported overlapping copper fragments so the board is not left with known shorting trace pieces.
What remains:
- Finish blocked dense nets:
RESET,PB1/MISO,PB2/SCK, LED anode, some 3.3 V/passive branches, and ground. - Re-run DRC/airwire checks.
- Likely adjust placement slightly around the ISP/ATtiny/passive cluster if those routes remain blocked.
Finish up quickly fast as you can no delay
Worked
I’m blocked: there are no available ACUs, so I can’t execute more routing or cleanup right now.
What I completed:
- Rechecked the current layout/routing state.
- Tried direct routing on the tight ATtiny85 ↔ ISP area.
- Re-ran placement optimization to open routing space around J4/ISP, U1, reset parts, and nearby passives.
- Final check after that showed the board is still not complete: 28 airwires, 12 dangling trace warnings, and 8 overlapping-copper errors remain.
What remains:
- Delete or repair the overlapping copper first.
- Finish routing the dense ISP/reset/pot/keep-alive nets.
- Finish ground and remaining 3.3 V / 5 V branches.
- Run final airwire/DRC checks before manufacturing export.
The layout is not ready for fabrication yet; once ACUs are available, the fastest path is copper cleanup first, then finish the remaining routes.
Locate copper errors
List remaining airwires
Fast routing order
Check placement nudges
Board Bring-Up Plan — Cat Deterrent Sprayer
Prerequisites
- Equipment: multimeter, oscilloscope, current-limited 5 V bench supply, AVR ISP programmer, USB power bank intended for final use.
- Firmware: see the Firmware Starter project file.
- Safety: start with pump disconnected; use a current limit before first power-up. The pump rail can draw up to the design assumption of 1.5 A peak.
1. Visual Inspection
- Check U1 ATtiny85 orientation.
- Check U2 MCP1700 orientation.
- Check Q1 AO3400A orientation.
- Check D1 flyback orientation: cathode to VBUS_5V / pump positive, anode to PUMP_SW / MOSFET drain.
- Check polarized C6 orientation if using electrolytic/polymer footprint.
- Verify optional DNP parts Q2, R5, D2, and F1 are populated only if intended. If F1 is DNP, bridge or populate an appropriate series link so VBUS_5V is powered.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Tolerance | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|---|
| VBUS_IN_RAW | J1 pin 1 | 5.0 V | supply dependent | J1 / F1 P1 | 100 mA initial, then higher for pump | No short to GND |
| VBUS_5V | F1 P2 | 5.0 V minus protection drop | supply dependent | TP1 | 100 mA initial | Present after F1/link |
| 3V3_LOGIC | U2 VO | 3.3 V | +/-5% for bring-up | TP2 | <50 mA expected without pump | 3.135 V to 3.465 V |
| GND | J1 pin 2 | 0 V | reference | TP3 | n/a | Common return continuous |
Procedure:
- With no power, measure resistance from VBUS_5V to GND and 3V3_LOGIC to GND.
- Power J1 from a current-limited 5.0 V bench supply with pump disconnected.
- Confirm TP1 is near 5 V and TP2 is near 3.3 V.
- Check for hot parts or excessive current before connecting pump.
3. Critical Signal Verification
Table
| Signal | Net | Expected State | Measure At | Notes |
|---|---|---|---|---|
| Reset | RESET | High near 3.3 V idle | U1 pin 1 or J4 RST | R3 pulls up; C7 filters |
| PIR output | PIR_OUT | Low idle, high on motion | TP4 | Depends on AM312 module behavior |
| Pump gate | PUMP_GATE | Low at reset/idle | TP5 | R2 pulls gate low |
| Pump switch node | PUMP_SW | Near 5 V off, near 0 V on | TP6 | With pump connected |
| Keep-alive gate | KA_EN_ISP_SCK | Low unless firmware pulses | Q2 gate | DNP branch by default |
Procedure:
- Verify RESET stays high during idle.
- Verify TP5 is low after reset and during ISP programming.
- Force PIR_OUT high with the sensor or a safe 3.3 V jumper and confirm firmware response.
4. Connector and Interface Tests
Table
| Connector | Pins | Test Method |
|---|---|---|
| J1 power input | P1=VBUS_IN_RAW, P2=GND | Continuity and polarity check before power |
| J2 pump | P1=VBUS_5V, P2=PUMP_SW | Verify diode polarity and MOSFET switching before pump install |
| J3 PIR | Pin_1=3V3_LOGIC, Pin_2=PIR_OUT, Pin_3=GND | Verify purchased AM312 module pinout before plugging in |
| J4 AVR ISP | VCC, GND, MOSI, MISO, SCK, RST | Continuity to U1 pins and programmer target detection |
5. Programming and Debug Interface
Table
| Interface | Signals | Connector | Tool |
|---|---|---|---|
| AVR ISP | MOSI/PB0, MISO/PB1, SCK/PB2, RESET/PB5, VCC, GND | J4 | USBasp or AVR ISP |
Procedure:
- Power board from current-limited 5 V input or programmer VCC if supported.
- Connect ISP to J4.
- Read ATtiny85 device signature.
- Flash starter firmware.
- Confirm startup LED blink.
6. Functional Validation
Table
| Test | Components | Input | Expected Output | Pass Criteria |
|---|---|---|---|---|
| LED | U1, R4, LED1 | Firmware startup | LED blinks | Visible blink, no excess current |
| PIR input | J3, U1 | Motion or logic-high test | Firmware sees PIR_OUT | Spray command only after trigger |
| Pump gate | U1, R1, R2, Q1 | Firmware spray command | TP5 rises to about 3.3 V | Gate returns low after burst |
| Pump switch | Q1, D1, J2, C5/C6 | Pump connected | PUMP_SW pulls low while on | No MCU reset or rail collapse |
| Keep-alive optional | Q2, R5 | ENABLE_KEEPALIVE firmware true | Pulsed load current | Only if selected power bank sleeps |
7. Expected Measurements Reference
Table
| Measurement | Location | Expected Value | Instrument |
|---|---|---|---|
| 5 V input | TP1 to TP3 | about 5.0 V | DMM |
| 3.3 V logic | TP2 to TP3 | about 3.3 V | DMM/scope |
| Pump gate high | TP5 to TP3 | about 3.3 V | Scope |
| Pump switch on | TP6 to TP3 | <0.2 V at <=1.5 A | Scope |
| Pump switch turn-off clamp | TP6 to TP3 | about VBUS + Schottky drop, far below 30 V | Scope |
Power Bank Idle Test
- Run board armed but idle longer than the selected bank's normal sleep timeout.
- If power shuts off, either use an always-on bank or populate/tune Q2/R5 keep-alive.
- Confirm keep-alive pulse resistor temperature and average current before enclosure use.
Pass/Fail Summary
Table
| Test Section | Result | Notes |
|---|---|---|
| Visual Inspection | [ ] Pass / [ ] Fail | |
| Power Rails | [ ] Pass / [ ] Fail | |
| Critical Signals | [ ] Pass / [ ] Fail | |
| Connectors | [ ] Pass / [ ] Fail | |
| Programming | [ ] Pass / [ ] Fail | |
| Functional Validation | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for enclosure test / [ ] Requires rework
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug Interface
6. Functional Validation
7. Expected Measurements Reference
Power Bank Idle Test
Pass/Fail Summary