Project Specification
Final follow-up correction — 2026-10-06
Supersedes older OE LOW/U4 unwired/count/check descriptions:109 components/112 nets. U13 OE now receiver-aware Q1/R1/R2/R3 fully-off disconnect; robust3.1V-valid partial-rail control remains unaccepted. U4 mapping/pad-order source verified and four rails wired, grounds remain isolated. IC2 misplaced centerVREF pad corrected by local selector override; selected copper check no findings. ERC14 Errors/0 Warnings. Flat-load budget now651.055mA MAIN_3V3 provisional allowance with explicit12mA CH340C; no sizing approval. Details and per-item blockers in connection-implementation-review; bench/mechanical/TVS/battery/machine/power-off release gates still apply.
Authoritative architecture revision — 2026-10-06
This section SUPERSEDES every single-port PROGRAM/CHARGE switch, original U1 module preservation, open MCU supply and export-continuity statement below. Older sections are historical baseline only. Current design is105 components/110 net identifiers and remains NOT FABRICATION READY.
- Dedicated charging J2 → F2/D3/D6 → U11. Charging CC1/CC2 have independent R31/R32 Rd. Charge data goes only to U11; C30/C38/C39 remain on CHARGER_VBUS.
- Separate programming J3 → F1/D4/D5; VBUS → U16 TLV760 logic-only USB_3V3 → U13. U13 is permanently port2 selected; S1/U6 removed. Original U1 removed and replaced with flat U14 ESP32-WROOM-32U, preserving external-antenna variant and all14 GPIO assignments. U15 CH340C and U14 are MAIN_3V3 powered, never program VBUS powered.
- U15 UART0 plus Q3/Q4 cross-coupled reset/boot support captured; R14/R30 are NEW reused-designator10k support parts, not obsolete switch/enable parts. C24/C25 are new generic bypass parts, not old guide capacitors superseded by C54/C55.
- USB and receiver positive rails are distinct. Power-off signal backfeed is NOT proven: OE tied LOW can pass host data to unpowered U15. This is a release blocker requiring mux disable/tolerance verification and off-state measurements.
- Direct MCU pin continuity is verified at schematic membership level; no hardware flash/test performed. U4 remains unwired; main/isolated grounds separate. Latest ERC26 Errors/0 Warnings; selected DRC2 VREF copper Errors and4 pre-existing clearance-only component Warnings. Detailed evidence/status is in connection-implementation-review.
- Targeted staging moved only15 new parts into existing160×100mm four-layer board; no resizing/routing or final layout approval. Enclosure access now needs TWO vertical USB-C openings, no S1 opening. Mechanical dimensions and RF/connector fit remain unapproved.
Current success criteria: resolve power-off backfeed, U4 mapping/pads, TVS/fuse/footprint audits and remaining justified checks; validate power/thermal/battery/machine requirements and approved command policies before bench/machine/manufacturing release. Prior editable-module blocker is superseded, not still required.
Historical pre-revision baseline
Status: DRAFT / REVIEW, not approved for fabrication. Date2026-10-06. Grounded in supplied connection guide and current89-component/97-net host design.
Project Overview
Receiver intended to accept wireless commands and produce an isolated analog control signal for a welding interface. Host circuitry is electrically captured; U1 internal export continuity/power/USB integration and U4 supply remain incomplete. Not an operational remote or certified safety device.
Intended Use
Prototype bench validation before any machine connection. Welding model, remote connector protocol, allowable command range and environmental limits require owner approval. Keep welding power disabled during all interface characterization.
What the Device Should Do
- Receive intended LoRa commands through E22-900M22S and ESP32 controller.
- Convert approved commands through isolated I2C and MCP4726 DAC/amplifier to machine interface.
- Operate from intended two-cell battery and support physical PROGRAM/CHARGE USB selection.
- Monitor battery divider and charger STAT/PG host signals.
- Define startup, lost-link, reset, stale-message and fault behavior with user; no analog-command policy selected automatically.
Main Features
LoRa antenna contact J1; ESP32 inherited module; battery/NTC inputs; USB mux and charger enable switch; dual fixed bucks; isolated power and data boundary; gain-two analog amplifier with series1k output resistor. Loaded output is not automatically exact0–10V.
Mechanical System Architecture
Battery/probe cables → CN2/CN1 → Receiver PCB → U9 → machine remote harness
External antenna/coax → J1; USB access and S1 mode switch require enclosure openings
No enclosure/board dimensions, mounting or connector positions approved. Cable orientation and purchased-part pad geometry require physical audit. No placement/routing altered in this work.
Electrical System Architecture
USB raw → F1/D5 → U6 → BQ25886 ↔ battery CN2
USB data → D4 → U13 → charger OR inherited USB-UART (exports blocked)
BQ25886 SYS → U10 3V3 → ESP32 intended / E22 / U2 main side
→ U7 5V → U4 intended isolated24V (disconnected)
U4 intended24V → OPA197; → U5 isolated5V → U2 isolated side / MCP4726
ESP32 → SPI radio; I2C → U2 → DAC → OPA197 → R9/U9
Hardware Subsystems
Charger retains guide resistor/NTC topology and support capacitors; actual battery charge acceptance unapproved. Bucks sense output after inductor. Radio host connections captured, actual MCU export continuity unverified. Isolated amplifier/DAC captured but unpowered due U4. USB architecture preserves PROGRAM/CHARGE intent, not a second USB bridge/connector redesign.
Interfaces and Connections
CN2 pin1 BAT_PLUS/pin2 GND; CN1 TS/probe and main GND; U9 pin1 ANALOG_OUT, pin2 ISO_GND, pin3 NC. These are schematic assignments, not verified cable face numbering. GND and ISO_GND remain separate. J1 center RADIO_ANT, outer contacts main GND. Firmware file records all used host GPIOs.
Power and Runtime Expectations
Intended two-cell architecture is provisional; capacity, BMS arrangement, cutoff, charge and thermal limits unresolved. No runtime target accepted. Simultaneous full nominal charge and provisional peak load exceeds resistor-derived USB current allowance; battery supplement/charge reduction requires characterization.
Power Tree and Power Budget
See power-budget file for evidence and provisional calculations: MAIN_3V3639mA; MAIN_5V200.116mA; ISO_5V24.625mA; SYS3.758W/626mA at6V. These are design allowances, not guaranteed maxima or safety approval. U5 estimated0.468W dissipation at24V is a thermal concern.
Manufacturing and Assembly Expectations
No fabrication/export release. Preserve replacement designators C52–C58; equivalence to guide C24–C28/C36/C37 documented. R24 external probe excluded from PCB/pick-and-place, not duplicated onboard. Actual footprint drawing audits, effective capacitance and component derating remain required. Assembly vendor/layer count not selected here.
Firmware-Relevant Hardware Requirements
Host pin mapping documented, internal continuity unverified. Firmware starter is documentation only, not built or ready-to-flash. Need authenticated/paired command protocol, stale/replay detection and diagnostics. DAC EEPROM power-up state must be inspected against approved startup policy; no automatic command selected.
Physical Design Expectations
Maintain isolation boundary and eventual creepage/clearance for selected working voltage; antenna placement/coax access/EMI require later layout work. No mains connection assumed or permitted. Welding transient immunity and connector compatibility unresolved.
Important Design Decisions
Preserve original U1 identity; leave +3V3/+5V open to avoid unsplit-rail/backfeed risk. U4 remains wholly disconnected without authoritative mapping and actual pad geometry. Preserve isolated return separation. Never hide missing power with flags before integration. Fifteen host groups annotated; spatial drafting blocked by unavailable arrangement API, replacement symbols overlap at origin.
Assumptions
Two-cell battery, nominal24V isolated supply and intended analog control follow current guide/part architecture, not verified battery or machine acceptance. Output load, environment, legal RF region, antenna gain and startup/link-loss policy are open user decisions. No safety isolation rating inferred from the presence of isolator parts.
Change Notes
Host connection capture completed in prior batch; canonical passive roles and all host groups added in follow-up. Specification, provisional power analysis, bench bring-up, firmware starter and regulatory planning added. ERC remains34 Errors/0 Warnings; overall design remains partial.
Success Criteria
Editable module integration/MCU continuity confirmed; U4 exact mapping and pads audited; physically correct cable/switch/TVS orientation; reviewed battery and machine requirements; approved command policies; justified clean ERC; readable schematic; power/thermal/transient bench tests; regulatory path established before layout/fab release.