Temperature and Humidity Sensor Node Design

flux

0:00

Work completed
  • Decoupling capacitor C1: set to 100 nF, connected between U2 VCC and GND within 5 mm
  • Decoupling capacitor C2: set to 100 nF, connected between U2 AVCC and GND within 5 mm
  • Bulk capacitor C3: set to 10 µF, connected between U2 VCC and GND within 5 mm
  • Pull-up resistor R1: set to 10 kΩ, connected between U2 RESET and VCC
  • Protected 5 V entry circuit: oriented D1, TVS, and PTC with TVS breakdown > 5.25 V
  • Sabertooth headers: J2 Pin 1→U2 PD5, J3 Pin 1→U2 PD6; Pin 2 of each to GND
  • Encoder connectors: removed incorrect GND ties; J4 Pin 1→U2 PC4, Pin 3→U2 PC5, Pin 2→GND; J5 Pin 1→U2 PD2, Pin 3→U2 PD3, Pin 2→GND
  • AREF decoupling capacitor C4: 100 nF, connected between U2 AREF and GND within 5 mm
  • Pull-up resistors R2 and R3: each 10 kΩ, applied to ENC1_A and ENC1_B
  • ERC review passed with no errors and added to project property ERC_Review
  • Project properties set: Lock Net Names = true; Ground Pour Convention = “Pour ground on layers L2 and L3 with thermal spokes”; Initial Placement Approach = “Auto-Layout placement”
Success criteria review
  • ✅ All power, reset, and signal nets correctly connected with decoupling and bulk caps as specified
  • ✅ Sabertooth and encoder connectors properly mapped, no erroneous GND ties
  • ✅ ERC passed with no errors; schematic approved for PCB layout ground pour and placement
Next step Proceed to the PCB editor to apply ground pour on layers L2/L3 and run Auto-Layout placement of components.
160 days
certy

certy

why is J1 not connected
160 days

flux

1:48

Accessing knowledge base.

Analyzing the schematic.

Analyzing the schematic.

Short answer: J1 is the in-circuit programming header placeholder, but it hasn’t been wired to the ATmega’s ISP signals yet.
Details:
  • J1 is a 6-pin single-row header marked “ICSP,” but no nets are assigned to its pins in the schematic.
  • To make it functional, it must be connected to U2 as follows (AVR ISP 6-pin mapping):
    • Pin 1 → U2: PB4 (MISO)
    • Pin 2 → VCC
    • Pin 3 → U2: PB5 (SCK)
    • Pin 4 → U2: PB3 (MOSI)
    • Pin 5 → U2: RESET/PC6 (and keep R1 10 kΩ pull-up to VCC)
    • Pin 6 → GND
Optionally, we can swap J1 to the standard keyed 2x3 AVR ISP footprint for tooling compatibility: 2x3 Pin Header.
Want me to wire J1 per the mapping above and, if you prefer, replace it with a keyed 2x3 header?
Header wiring help
Search keyed ISP header
Replace J1 footprint
Confirm mapping nets
160 days
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