Schematic Audit — Check My Work
Date: 2026-05-02
Scope: Read-only audit of the current Pi Zero 2 W Power HAT schematic after the user’s manual wiring pass. No project edits were made.
Overall Status
The main topology is close, but the schematic is not yet clean. Key rails and signal paths are mostly present, but there are several items that still need attention before layout:
- 39 PCB airwire DRC errors remain. These are layout/routing issues, not necessarily schematic connectivity errors.
- ERC floating-pin warnings remain for
J6:C, several test points, expected-unused Pi header pins, and a 6V:P1 object.
TP3 / Net 22 is still a single-pin net.- Some net names are still unnamed or generic even though the connections appear correct.
Q2_GATE rename did not take; the actual Q2 gate net is still called AUTO_NAME.
What Looks Correct
Barrel Jack and Raw 6 V Rail
Current live netlist shows:
J6:A is on the raw 6 V input rail with U2:VIN, U2:EN, input capacitors, D5:K, D2:K, J1:P2, J2:P2, and C6:1.J6:B is on the common ground net.
This matches the intended Tensility mapping:
J6:A -> VIN_6VJ6:B -> GNDJ6:C -> NC / plug-detect if used
Issue: the raw 6 V rail is currently shown as an unnamed net in the live schematic output, even though the intent is VIN_6V. Rename/label this net back to VIN_6V if it is not visibly labeled in the editor.
Buck Switch Node
The SW node is now present and correctly contains:
This addresses the earlier L2:1 floating issue.
Bootstrap Network
Bootstrap wiring appears structurally correct:
BOOT: U2:BOOT, R9:1BOOT_CAP: R9:2, C5:P1SW: U2:SW, C5:P2, L2:1
This means the bootstrap path is:
U2:BOOT -> R9 -> C5 -> SW
Buck Output / BUCK_5V
The post-inductor buck output node is present as an unnamed net containing:
This is the intended BUCK_5V rail. Rename/label this unnamed net to BUCK_5V if it is not visibly labeled.
Ground side of output capacitors:
Feedback Divider
Feedback net is correct:
FB: U2:FB, R6:2, R7:P1R7:P2 -> GNDR6:1 -> BUCK_5V node
Values/properties:
This matches the ~5.2 V target from the corrected topology.
eFuse / Pi 5 V Path
The Pi power path appears correct:
BUCK_5V node -> F2:1F2:2 -> U1_INU1_IN: F2:2, U1:IN pins, U1:EN/UVLOPI_5V: U1:OUT, H1:Pin_2, H1:Pin_4, D1:1, R10:P2
This matches the intended path:
BUCK_5V -> F2 -> TPS259531 eFuse input -> PI_5V -> H1 pins 2 and 4
eFuse dVdt and FLT Support
The newly added support networks now exist:
U1:dVdt connected to C7:P2C7:P1 -> GNDU1:~FLT connected to R10:P1R10:P2 -> PI_5V
This resolves the previous real omissions for dVdt and ~FLT.
Motor Low-Side Switches
Motor channel low-side topology is present:
Channel 1:
MOTOR1_LOW: Q1:D, D2:A, J2:P1D2:K is on raw 6 V railQ1:S -> GNDQ1_GATE: Q1:G, R1:2, R3:1R3:2 -> GNDPWM10: H1:Pin_19, R1:1
Channel 2:
MOTOR2_LOW: Q2:D, D3:A, J1:P1D3:K is on raw 6 V railQ2:S -> GND- Q2 gate net:
AUTO_NAME: R2:1, R4:1, Q2:G
R4:2 -> GNDPWM17: H1:Pin_11, R2:2
This is electrically correct. Only the Q2 gate net name needs cleanup.
LED GPIO Connectors
LED connector nets are correct:
GPIO24_LED: H1:Pin_18, J5:Pin_1GPIO25_LED: H1:Pin_22, J7:Pin_1J5:Pin_2 -> GNDJ7:Pin_2 -> GND
Role notes correctly state these are for LED modules with built-in current limiting; bare LEDs need series resistors or drivers.
Common Ground
The common ground net includes:
J6:BU2:GNDU1:GND, U1:EPQ1:S, Q2:S- Pi ground pins including
H1:Pin_6, Pin_9, Pin_14, Pin_25, Pin_34, Pin_39
C1:P2, C2:P2, C3:2, C4:2, C6:2R3:2, R4:2, R7:P2, R_ILM:P2J5:Pin_2, J7:Pin_2
This matches the single common ground requirement.
What Still Needs Attention
1. Net Names / Labels Need Cleanup
The live schematic still shows these important rails as unnamed nets:
- Raw input rail containing
J6:A, U2:VIN, U2:EN, D5:K, D2:K, J1:P2, J2:P2, etc. This should be labeled VIN_6V.
- Buck output node containing
L2:2, C3:1, C4:1, F2:1, R6:1. This should be labeled BUCK_5V.
- Main ground net is unnamed in the live output, although it is functionally GND. Make sure it is labeled
GND in the editor.
2. Q2 Gate Net Name
Electrical connection is correct, but the net name is still AUTO_NAME:
AUTO_NAME: R2:1, R4:1, Q2:G
Rename this net to Q2_GATE after removing any conflicting duplicate Q2_GATE portal/label.
3. J6:C Floating
ERC reports:
If unused, place a No-Connect marker on J6:C. Do not tie it to VIN or GND unless you intentionally use the jack switch/contact behavior.
4. Test Points / Single-Pin Nets
ERC reports floating test points:
Single-pin net warning:
Net 22 has only one pin connected: TP3:-
Action: either connect each test point to the intended rail/signal or mark/remove it. Likely assignments could be:
TP1 -> VIN_6VTP2 -> BUCK_5VTP3 -> PI_5VTP4 -> GND
But verify intended labels/placement before wiring.
5. 6V:P1 Floating
ERC reports:
This appears to be a leftover power symbol/portal/object. Either connect it to VIN_6V intentionally or remove/NC it if it is a stale artifact.
6. Pi Header Floating Pins
Many unused Pi header pins are floating. That is expected if they are not used, but ERC will continue warning unless you mark unused H1 pins as No-Connect or accept the warnings.
Used H1 pins currently include:
Pin_2, Pin_4: PI_5VPin_6, Pin_9, Pin_14, Pin_25, Pin_34, Pin_39: GNDPin_11: PWM17Pin_18: GPIO24_LEDPin_19: PWM10Pin_22: GPIO25_LED
7. DRC Airwires
DRC reports 39 airwire errors. These are PCB layout routing issues, not necessarily schematic net problems. Once the schematic cleanup items above are handled, the board still needs physical routing or autorouting.
8. Parts Availability
Manufacturer Part Number review passes. Parts Available review is currently unrun, so availability has not been reconfirmed after the latest changes.
Recommended Fix Order
- Label unnamed rails:
- raw input rail ->
VIN_6V
- buck output node ->
BUCK_5V
- common ground ->
GND
- Rename
AUTO_NAME -> Q2_GATE after clearing duplicate label conflict.
- Mark
J6:C No-Connect.
- Resolve test points:
- connect them to intended rails/signals or remove/NC them.
- Remove or connect
6V:P1 artifact.
- Decide whether to mark unused H1 pins NC or accept warnings.
- Re-run ERC.
- Run Parts Available review.
- Proceed to PCB routing to clear 39 airwires.
Bottom Line
Your main functional wiring looks correct now. The remaining work is mostly cleanup and ERC hygiene: net labels, NC markers, stale artifacts/test points, Q2 gate naming, and then PCB routing.