ESP32-S3 Firmware Refinement
Diagram
Table
| Interface | Connector/Net | Notes |
|---|---|---|
| 12V input | J2 | Pin 1 = +12V, pin 2 = GND assumption |
| USB data | J1 | D+/D- only to ESP32 native USB; VBUS is not tied to board power |
| Relay dry contact | J3 | Pin 1 = COM, Pin 2 = NO, Pin 3 = NC |
| Relay control GPIO | ESP32 IO4 | Drives MOSFET gate through 100 ohm resistor |
| Boot | ESP32 IO0 | BOOT button pulls low |
| Reset/enable | ESP32 EN | RESET button pulls low |
Table
| Rail | Load | Estimated Current |
|---|---|---|
| 3.3V | ESP32-S3 WiFi peaks | 500mA design peak |
| 12V | Relay coil ACNM1112 | 53.3mA rated |
| 12V | Buck input for 3.3V rail | About 162mA at 3.3V/500mA, 85% efficiency |
| 12V | Total design peak | About 216mA plus margin |
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Power
Compute and USB
Relay Output
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes