Arduino ESP32 Circuit Board Design

flux

Work done
  • Built the full schematic architecture around U1, PS1, U2, and U3 with mains input protection, isolated 5 V, local 3.3 V, one RTD interface, and 8 SSR control channels.
  • Added and wired eight SSR paths using K1-K8 plus Q1-Q8, with fused mains distribution, neutral return, and ESP32 GPIO control lines.
  • Added mains protection and conversion with F1, F2, RV1, and PS1.
  • Configured a 160 mm x 100 mm 4-layer layout with 6 mm board inset / keep-out margin for initial mains segregation and thermal routing space.
  • Updated Design Notes with the chosen GPIO mapping, power architecture, safety constraints, and the connector limitation.
Success criteria review
  • ✅ The schematic now includes the required subsystems: ESP32 control, AC input power conversion, 8 SSR channels, and an RTD measurement front-end.
  • ✅ The power tree derives isolated 5 V from mains and local 3.3 V for logic using PS1 and U2.
  • ✅ Each SSR channel is implemented with isolated optotriac drive and a 25 A class triac device.
  • ⚠️ The layout framework is set up for high-voltage separation, but the currently placed output/input terminal blocks U4-U13 are still placeholders and do not satisfy the final >=20 A connector requirement.
  • ⚠️ The RTD connector U13 is presently a simplified placeholder connection, and several optional/snubber parts remain intentionally unwired, which is why ERC still reports floating pins on unfinished support parts.
Next steps
  • Replace U4-U13 with final >=20 A mains-rated connectors, then finish the remaining snubber / RTD support wiring and do a final ERC cleanup.
  • If you want, I can continue by tightening the SSR snubber network, correcting the RTD front-end to a proper 2-wire or 3-wire MAX31865 topology, and preparing the board for placement/routing.
Fix RTD and snubbers
Upgrade power connectors
Clean up ERC issues
Set layout rules
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Files

Schematic

Layout

3D View

Design Notes
Architecture
  • Mains input: 220 VAC nominal with +/-15% tolerance.
  • Protection: PCB fuse holder with cartridge fuse, MOV across line and neutral, isolated AC-DC module.
  • Low-voltage rail: isolated 5 V rail from AC-DC module for controller and accessories.
  • Logic rail: local 3.3 V LDO from 5 V for ESP32 and RTD interface.
  • Controller: ESP32-WROOM module.
  • Outputs: 8 isolated AC SSR channels implemented as zero-cross optotriac plus 25 A triac per channel.
  • RTD input: MAX31865 SPI RTD front-end for one RTD connector.
Wiring choices
  • ESP32 SSR outputs:
    • IO32..IO27, IO14, IO13, IO15 used as SSR1..SSR8 control GPIOs.
  • ESP32 RTD SPI:
    • IO18 -> SCLK
    • IO23 -> MOSI
    • IO19 -> MISO
    • IO5 -> CS
    • IO4 -> DRDY
  • ESP32 boot control:
    • EN pull-up to 3.3 V with 100 nF to GND
    • IO0 pull-up to 3.3 V for default normal boot
  • MAX31865 configured as a single RTD front-end on 3.3 V.
Safety and layout constraints
  • Maintain minimum 6 mm clearance and creepage between mains and low-voltage circuitry.
  • Maintain minimum 3 mm clearance between AC line and neutral copper.
  • Add routed isolation slot between mains switching zone and controller zone.
  • Keep all AC mains copper on outer layers only.
  • Use very wide copper, polygons, or off-board current handling strategy for 20 A paths.
  • Treat the currently selected terminal blocks as provisional because library current rating is below the design requirement.
Known limitations to resolve in layout/BOM review
  • The selected 2-position terminal block is a schematic placeholder and does not satisfy the final >=20 A interconnect requirement.
  • SSR thermal design must assume external heatsinking or large copper area for sustained high current.
  • Snubber values and per-channel surge suppression remain to be finalized.

  • Architecture

  • Wiring choices

  • Safety and layout constraints

  • Known limitations to resolve in layout/BOM review