Schematic Design Review Issues

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b3dn

Perform an analysis of the provided schematic for real, schematic-level design issues.
Your review should include, but not be limited to:
Electrical and Logical Issues
  • Incorrect net connections or floating nets
  • Incorrect or missing pin assignments
  • Connectivity errors across schematic sections
Component-Level Review
  • Missing or misplaced components
  • Absence or incorrect placement of decoupling capacitors
  • Incorrect or missing pull-up/pull-down resistors
  • Absence of current limiting resistors on LEDs or other sensitive components
Power and Signal Integrity
  • Inadequate power distribution (missing bypass paths, star grounding, etc.)
  • Potential signal integrity issues (improper termination, excessive trace length without buffering, etc.)
Schematic Best Practices
  • Incorrect or inconsistent net labeling
  • Lack of annotation for key nets or nodes
  • Confusing or ambiguous signal flow
Instructions
  • Do not speculate or provide hypothetical examples.
  • Focus only on issues observed directly in the provided schematic.
  • Offer actionable corrections and design optimizations where appropriate.

flux

0:22

Thought for 4 sec

Thought for 4 sec

Thought for 5 sec

Thought for 4 sec

Thought for a moment

I’ll audit the current schematic for concrete connectivity, component, power, and signal-integrity issues. I’ll read the design data and review results first, then create a concise findings report in the project files with actionable corrections only for issues directly observed.

flux

0:57

Thought for 4 sec

Created 4 tasks.

1/4 Collect schematic overview, key component details, BOM summary, and ERC review results

Thought for 3 sec

Completed design checks — found 491 issues.

Read schematic.

Read BOM.

Read schematic.

Thought for 7 sec

2/4 Inspect power, ESP32, ADC, isolated RS-485, connectors, and passives for concrete schematic issues

Thought for a moment

Initial review data is loaded. I found a large DRC airwire set, but I’m continuing with schematic-level checks now so the report separates real schematic problems from layout-only routing status.

flux

6:07

Thought for 6 sec

Completed design checks — found 491 issues.

Completed 6 design checks — found 491 issues.

Read schematic.

Read schematic.

Thought for 11 sec

Read U1 datasheet for ESP32-S3-WROOM-1 module power supply pin.

Read U2 datasheet for ADS131M08 external clock input XTAL1 CLK.

Read U5 datasheet for AP63357 recommended application circuit .

Read U6 datasheet for ADM2587E recommended circuit VCC GND1 Vi.

Read "[Datasheet for ADM2587EBRWZ, Analog Devices Inc.] ADM2587E recommended circuit VCC GND1 Visoout Visoin GND2 decoupling isolated ground capacitors A B Y Z connections" in ADM2582E_2587E.pdf.

Read ADM2582E_2587E.pdf.

Thought for 7 sec

3/4 Write actionable schematic review findings to a project file

Thought for 1 min

Thought for 3 sec

4/4 Summarize findings and link the project file

Thought for 3 sec

4/4 tasks completed.

Thought for a moment

Completed the schematic-level review and created the full findings report here: Schematic-Level Design Review.
Key observed issues: U1 3V3 is floating, Y1 GND is floating, C46/C71 are shorted on RS485_ISOGND, and CT10_P_RAW appears to incorrectly short many CT input channels together. I also noted cleanup items for unused ESP32 GPIOs, ADC NC pins, and floating J4 pins 21–24.
Fix floating power
Correct CT net
Fix shorted capacitors
Rerun ERC/DRC
Document corrections
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Schematic-Level Design Review
Date: 2026-05-29
Project: Home Energy Monitor
Scope
This review focused only on issues directly visible in the current schematic/netlist and current ERC/DRC outputs. It does not include hypothetical failure modes or layout-only optimization except where the schematic creates a layout/routing consequence.
Reviewed Sources
  • Current schematic summary: 663 schematic items, 102 nets.
  • Key components inspected: U1 ESP32-S3-WROOM-1-N16R8, U2/U3/U4 ADS131M08, U5 AP63357DV-7 buck regulator, U6 ADM2587EBRWZ isolated RS-485 transceiver, J1/J2/J3/J4/J5/J6, Y1, FB1, L1, regulator/ADC/RS-485 support passives.
  • Current ERC/DRC review output timestamp: 2026-05-29T08:04:22Z.
  • Datasheet checks used for observed issues: ESP32-S3-WROOM-1, ADS131M08, AP63357/AP63357, ADM2582E/ADM2587E.
Critical Schematic Issues
1. ESP32 3V3 power pin is not actually connected to the 3V3 rail
Observed evidence
  • ERC reports: Floating pin: U1:3V3.
  • The 3V3 net contains buck output and many loads, including ADS131M08 supplies, Y1 Vdd, U6 VCC, decoupling capacitors, and R183, but it does not list U1:3V3 as a connection.
  • U1 pin list includes 3V3::2, and the ESP32-S3-WROOM-1 datasheet identifies pin 2 as the power supply pin with a 3.0 V to 3.6 V operating range.
Impact
The ESP32 module is unpowered at schematic level even though its EN, UART, SPI, and RS-485 control nets are connected. The board will not boot or communicate.
Actionable correction
Connect U1:3V3 to the 3V3 net. Keep C30 100 nF and the existing bulk capacitance on the same 3V3 rail, and ensure at layout that C30 is placed close to U1 pin 2/GND.
2. Oscillator Y1 ground pin is floating
Observed evidence
  • ERC reports: Floating pin: Y1:GND.
  • ADC_MCLK connects Y1:OUT to U2/U3/U4:XTAL1/CLKIN.
  • 3V3 connects Y1:Vdd and Y1:EN.
  • The GND net does not list Y1:GND.
Impact
The ADS131M08 clock source has power and output wiring but no ground return. The oscillator cannot operate reliably, so all three ADCs may lose their master clock.
Actionable correction
Connect Y1:GND to GND. If Y1 is an 8.192 MHz oscillator as indicated by its role details, keep Y1:OUT on ADC_MCLK and Y1:Vdd/Y1:EN on 3V3.
3. RS-485 isolated-side decoupling capacitors C46 and C71 are shorted across the same net
Observed evidence
  • ERC reports:
    • Component shorted. Both pins of C71 are connected to the same net. (net: RS485_ISOGND)
    • Component shorted. Both pins of C46 are connected to the same net. (net: RS485_ISOGND)
  • RS485_ISOGND net explicitly contains C71:P1, C71:P2, C46:P1, and C46:P2.
  • The ADM2587E datasheet requires VISOOUT/VISOIN-side decoupling between isolated power and isolated ground, not both capacitor pins on isolated ground.
Impact
The intended isolated-side decoupling is absent. U6’s isolated supply has no effective reservoir/bypass capacitance, which can cause RS-485 bus-side supply instability and EMI problems.
Actionable correction
Rewire C46 and C71 so one side is on the isolated supply path and the other side is on RS485_ISOGND:
  • C46 100 nF: connect between RS485_VISOOUT or the post-ferrite VISOIN supply node and RS485_ISOGND, matching the intended local bypass point.
  • C71 10 uF: connect between the isolated supply node and RS485_ISOGND as reservoir capacitance.
  • Keep U6 Visoout and Visoin connected through FB1 as currently intended, but do not short the decoupling capacitor terminals together.
4. The CT10_P_RAW net shorts a large group of CT connector inputs together
Observed evidence
  • Net CT10_P_RAW has 203 connections.
  • It includes multiple unrelated connector pins and resistor inputs, for example: J3:18, J3:22, J4:2, J4:6, J4:8, J4:11, J4:15, J4:20, J4:19, J4:18, J4:17, J4:16, J4:14, J4:13, J4:12, J4:10, J4:9, J4:7, J4:5, J4:4, J4:3, J4:1, J3:24, J3:23, J3:21, J3:20, J3:19, J3:17, and many raw-side series/burden/filter resistor pins.
  • Other CT raw nets have the expected small structure, typically three connections: one connector pin, one burden half, and one series/filter resistor. Examples: CT1_P_RAW, CT1_N_RAW, CT2_P_RAW, CT2_N_RAW, CT3_P_RAW, etc.
Impact
This is a real schematic short across many CT inputs. It collapses numerous independent current-transformer channels into one common raw node, destroying channel isolation/independence and invalidating measurements for those channels.
Actionable correction
Split CT10_P_RAW into the intended per-channel raw nets. Each CT connector pin should connect only to its matching burden resistor half and its matching ADC input series/filter resistor. Use the existing naming pattern as the template: CTx_P_RAW and CTx_N_RAW should each have a small, channel-local connection set rather than a large shared bus.
5. ADS131M08 unused NC pins are not explicitly marked no-connect
Observed evidence
  • U2/U3/U4 each have an NC pin in the schematic symbol.
  • The ADS131M08 datasheet states NC may be left unconnected or connected to AGND.
  • The current ERC output does not report these pins as the major floating issue, but the schematic contains No Connect markers elsewhere and these ADC NC pins are not visible in the reviewed net list as intentionally marked.
Impact
This is not a functional wiring fault if the pins are truly left open, but it is ambiguous and can create review noise or assembly/debug confusion.
Actionable correction
Either mark U2:NC, U3:NC, and U4:NC as intentional no-connects, or connect them to AGND per the ADS131M08 datasheet option. Do not connect them to unrelated signal nets.
6. ESP32 unused GPIO pins are floating and not documented as intentionally unused
Observed evidence
ERC reports the following U1 pins floating: IO41, IO20, IO18, IO1, IO7, IO19, IO35, IO37, IO2, IO3, IO42, IO40, IO39, IO46, IO38, IO21, IO47, IO45, IO48, IO36.
Impact
Floating unused GPIOs are often acceptable for configurable MCU pins, but on this part several of the listed pins have special roles or constraints:
  • IO19/IO20 are USB D-/D+ capable pins.
  • IO3, IO45, and IO46 are strapping-related pins per the ESP32-S3 datasheet.
  • IO35/IO36/IO37 have module/PSRAM availability notes in the datasheet for some variants.
Leaving them unmarked makes the schematic ambiguous and keeps ERC warnings unresolved.
Actionable correction
For pins that are intentionally unused, add explicit no-connect markers and document the intended default boot behavior. For strapping pins, verify the default internal pull state supports the intended boot mode; add external pull resistors only where the desired boot/configuration state is not guaranteed by the module defaults or attached circuitry.
7. J4 pins 21 through 24 are floating without explicit no-connect intent
Observed evidence
ERC reports: Floating pin: J4:21, J4:22, J4:23, and J4:24.
Impact
If J4 is intended to expose CT inputs 13 through 24, unused/floating tail pins can confuse harness pinout documentation and assembly checks. If these pins are reserved, that intent is not explicit in the schematic.
Actionable correction
Either wire J4 pins 21 to 24 to the intended CT channels or mark them as intentional no-connects/reserved pins and update the connector role/pinout notes.
Power and Decoupling Observations
AP63357 buck regulator block
Observed evidence
  • U5 VIN and EN are on 12V_IN.
  • U5 SW connects to L1 and C28 bootstrap return via BUCK_SW.
  • U5 BST connects to C28 via BUCK_BST.
  • L1 output is 3V3.
  • Feedback network is present: R181 = 91 kΩ from 3V3 to FB, R182 = 30 kΩ from FB to GND, C29 = 33 pF feedforward, matching the AP63357 datasheet’s 3.3 V internal-compensation component table.
  • Input capacitor C25 = 10 µF from 12V_IN to GND; output capacitors C26/C27 = 22 µF each from 3V3 to GND.
  • U5 COMP is tied to GND, which matches the datasheet option for internal compensation.
Issue status
No schematic-level wiring fault was observed in the buck feedback/compensation network. The only power-tree issue observed is that U1 is missing from the generated 3V3 net.
ADS131M08 ADC blocks
Observed evidence
  • U2/U3/U4 AVDD and DVDD pins are connected to 3V3.
  • Each ADC has 1 µF supply decoupling represented on the 3V3/GND nets.
  • Each ADC CAP pin has a 220 nF capacitor to GND: C38, C39, C40.
  • Each REFIN pin has a 100 nF capacitor to GND: C41, C42, C43.
  • ADS131M08 datasheet requires AVDD/DVDD 1 µF decoupling and CAP 220 nF to DGND for DVDD > 2.7 V, which is consistent with the observed schematic.
Issue status
No missing ADC supply/CAP decoupling was observed at schematic-net level. Physical placement still must be handled during layout.
ADM2587E isolated RS-485 block
Observed evidence
  • U6 VCC pins are on 3V3 with C44 100 nF and C45 10 nF to GND.
  • U6 VISOOUT goes to FB1, and FB1 feeds RS485_ISOGND/Visoin-side area in the current netlist.
  • U6 GND2 pins and J6 pin 3 are on RS485_ISOGND.
  • C46 and C71 are shorted on RS485_ISOGND rather than connected from isolated supply to isolated ground.
Issue status
The RS-485 block has a real decoupling wiring error on C46/C71. Correcting those capacitors is required before treating the isolated bus supply as valid.
Signal-Integrity and Net-Labeling Issues Directly Observed
  1. CT10_P_RAW is misused as a massive shared net across many CT connector/filter inputs. This is both a logical short and a naming/labeling error.
  2. RS485_ISOGND currently includes both terminals of C46 and C71, which hides the intended isolated supply decoupling topology.
  3. The current DRC output reports 100 shown airwire errors out of a larger set. These are PCB routing/layout issues, not schematic connectivity faults by themselves, but the large CT10_P_RAW short will also create incorrect routing demand until fixed.
  1. Fix the critical functional power/clock errors:
    • Connect U1:3V3 to 3V3.
    • Connect Y1:GND to GND.
  2. Fix RS-485 isolated decoupling:
    • Rewire C46 and C71 between isolated supply and RS485_ISOGND.
  3. Split CT10_P_RAW into proper per-channel raw CT nets.
  4. Mark intentional unused pins:
    • U1 unused GPIOs.
    • U2/U3/U4 NC pins.
    • J4 pins 21 to 24, if reserved.
  5. Re-run ERC and then DRC/airwire review after schematic fixes. Do not route the PCB until the schematic-level issues above are corrected.
Summary of Observed Issues

Table

SeverityAreaObserved issueCorrection
CriticalPowerU1 3V3 pin floatingConnect U1:3V3 to 3V3
CriticalClockY1 GND floatingConnect Y1:GND to GND
CriticalRS-485 powerC46 and C71 both terminals shorted to RS485_ISOGNDRewire each capacitor from isolated supply to RS485_ISOGND
CriticalCT inputsCT10_P_RAW shorts many CT inputs togetherSplit into per-channel raw nets
MediumMCU annotationsMany unused ESP32 GPIOs floatingMark NC or add intentional strap/pull as needed
Low/MediumConnector annotationJ4 pins 21-24 floatingWire intended channels or mark reserved/NC
LowADC annotationADS131M08 NC pins not explicitly documentedMark NC or tie to AGND per datasheet

    Scope

    Reviewed Sources

    Critical Schematic Issues

    1. ESP32 3V3 power pin is not actually connected to the 3V3 rail

    2. Oscillator Y1 ground pin is floating

    3. RS-485 isolated-side decoupling capacitors C46 and C71 are shorted across the same net

    4. The `CT10_P_RAW` net shorts a large group of CT connector inputs together

    5. ADS131M08 unused NC pins are not explicitly marked no-connect

    6. ESP32 unused GPIO pins are floating and not documented as intentionally unused

    7. J4 pins 21 through 24 are floating without explicit no-connect intent

    Power and Decoupling Observations

    AP63357 buck regulator block

    ADS131M08 ADC blocks

    ADM2587E isolated RS-485 block

    Signal-Integrity and Net-Labeling Issues Directly Observed

    Recommended Fix Priority

    Summary of Observed Issues

Documents

    Project Specification

    Gateway Design Notes

    Schematic Organization Map

    Schematic-Level Design Review

Assets

No assets added.

Home Energy Monitor

Home Energy Monitor thumbnail
Panel-connected home energy monitor with non-invasive branch current sensing, whole-home power measurement, and smart outlet/switch integration for appliance-level energy visibility.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

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$25.66–$35.07

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$42.59–$43.70

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LCSC

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$65.73

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$11.56–$25.17

Controls