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Cardputer ADV RF NFC HAT Design Notes
Scope
Single M5Stack Cardputer ADV HAT integrating:
- CC1101 433 MHz sub-GHz module (
U2, VT-CC1101-433) - nRF24L01+ module with SMA (
U3, NRF24L01P-MODULE-SMA) - LoRa RA-02 433 MHz module (
U4) - PN532 NFC module header (
J2) using I2C - 3.3 V buck rail generated from the Cardputer ADV
5VOUTexpansion pin
Cardputer ADV power-source assumption
The HAT is powered by the M5Stack Cardputer ADV, not by an independent source.
Cardputer ADV EXT 2.54-14P pinout used:
Table
| J1 pin | Cardputer ADV signal | HAT net / use |
|---|---|---|
| 1 | G3 / RESET | SPI_CS_RA02 for RA-02 NSS, chosen as a reusable GPIO chip select |
| 2 | 5VIN | No connect; the HAT does not feed power into Cardputer |
| 3 | G4 / INT | SPI_CS_NRF24 for nRF24 CSN |
| 4 | GND | GND |
| 5 | G6 / BUSY | NRF24_CE |
| 6 | 5VOUT | 5VOUT_RAW, HAT power input from Cardputer |
| 7 | G40 / SCK | SPI_SCK |
| 8 | G8 / I2C_SDA | I2C_SDA |
| 9 | G14 / MOSI | SPI_MOSI |
| 10 | G9 / I2C_SCL | I2C_SCL |
| 11 | G39 / MISO | SPI_MISO |
| 12 | G13 / UART_RX | LORA_DIO0, chosen as LoRa interrupt/status GPIO |
| 13 | G5 / CS | SPI_CS_CC1101 |
| 14 | G15 / UART_TX | PN532_RST |
Power architecture
J1 Pin_6 / 5VOUT from Cardputer ADV feeds:F10ZCJ0075AF2E 750 mA resettable fuseD1SMF5.0A TVS to GNDU1TLV62568 1 A synchronous buck converter3V3rail for all RF/NFC modules
Buck converter design:
- U1 = TLV62568DBV
- C1 = 4.7 uF input capacitor on
5V_PROT - L1 = 2.2 uH buck inductor
- C2 = 10 uF output capacitor
- C7 = 47 uF shared 3.3 V rail bulk capacitor
- R1 = 453 kΩ, R2 = 100 kΩ feedback divider
- Formula from datasheet:
VOUT = 0.6 x (1 + R1/R2)-> about 3.318 V
Power budget
Approximate peak currents from module datasheets/library data:
Table
| Load | Peak current used for sizing |
|---|---|
| RA-02 LoRa TX | 97 mA |
| nRF24L01+ base IC | 13.5 mA RX / 11.3 mA TX; PA+LNA module may be higher depending module variant |
| CC1101 module | assumed under 50 mA typical module-level peak unless exact module datasheet provides otherwise |
| PN532 module/header | assumed under 150 mA depending external module/antenna board |
| Margin and simultaneous RF activity | reserve to 500 mA rail budget |
The 3.3 V regulator is sized as a 1 A buck to avoid overstressing the Cardputer 5VOUT and to provide margin. Firmware should avoid transmitting all RF modules at once unless Cardputer ADV 5VOUT current capability is confirmed.
Radio/NFC bus architecture
All SPI radios share
SPI_SCK, SPI_MOSI, and SPI_MISO:U2CC1101:CSN->SPI_CS_CC1101U3nRF24:CSN->SPI_CS_NRF24,CE->NRF24_CEU4RA-02:NSS->SPI_CS_RA02,DI00->LORA_DIO0,RESET->LORA_RESET
Biasing:
- R6 = 10 kΩ pull-up on CC1101 CSN
- R7 = 10 kΩ pull-up on RA-02 NSS
- R8 = 10 kΩ pull-up on nRF24 CSN
- R9 = 100 kΩ pull-down on nRF24 CE
- R5 = 10 kΩ pull-up on RA-02 RESET
PN532 header
J2 is wired for I2C:- J2 pin 1:
3V3 - J2 pin 2:
GND - J2 pin 3:
I2C_SDA - J2 pin 4:
I2C_SCL - J2 pin 6:
PN532_RST - J2 pins 5, 7, 8: intentionally unconnected for optional IRQ/mode/vendor-specific pins
- R3/R4: 4.7 kΩ I2C pull-ups to
3V3
RF layout cautions
- Place CC1101, nRF24, RA-02, and PN532 antenna areas apart to reduce coupling.
- Use a solid ground plane under RF modules, except where module antenna keepouts require copper clearance.
- Keep the CC1101 ANT trace to J3 SMA short and 50 ohm controlled-impedance if possible.
- Keep buck converter switching node
BUCK_SWshort and away from RF antennas and PN532 antenna wiring. - Place decoupling capacitors directly at each module power pin.
- Avoid simultaneous high-power RF transmit from multiple radios unless supply current and EMI are validated.
Validation status
Electrical-rule review returned no ERC categories after removing accidental duplicate modules and marking intentionally unused pins as no-connect.
Open items before PCB layout
- Confirm the exact PN532 module/header pinout to match the physical module you will plug into J2.
- Confirm Cardputer ADV 5VOUT current rating if you plan simultaneous RF transmission.
- Confirm whether the final HAT should use SMA, U.FL, or onboard antennas for each RF module.
Scope
Cardputer ADV power-source assumption
Power architecture
Power budget
Radio/NFC bus architecture
RF layout cautions
Validation status
Open items before PCB layout
