AHD to NTSC Video Converter Design

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Create a combined engineer handoff package from the current project files.
Include:
Video Architecture Decision Record
Project Specification
Board Bring-Up Plan
Current schematic shell summary
Open technical decisions
Supplier document request checklist
Connector pinout decision table
Preliminary BOM risk list
Add the following engineering decisions:
Treat NVP6321 as the first-choice provisional 1-channel AHD receiver, but do not wire it pin-by-pin until the real datasheet or reference schematic is available.
Treat CV2880 as the first-choice provisional scaler / NTSC CVBS encoder candidate because it appears to combine digital video input, scaling, frame/memory functions, and analog CVBS DAC output.
Treat ADV739x as a fallback encoder path only, because it is an encoder, not a full AHD downscaler solution, and ADV7393 is not recommended for new designs.
Keep ADA4430 as an optional CVBS reconstruction filter / driver stage. Do not mark it mandatory until the selected encoder’s DAC output circuit is verified.
Add a required I2C/configuration plan. Assume the AHD receiver and scaler/encoder may need initialization by MCU, EEPROM, or configuration header.
Do not proceed to PCB layout until the full video IC datasheets/reference designs, package fit, power budget, clocking, reset, I2C boot behavior, and connector pinout are confirmed.
For J2 pin 1, use a safe configurable design:
Default J2 pin 1 should be NC / DNP until the real vehicle-camera harness pinout is confirmed.
Add an optional protected 12 V pass-through path using a DNP 0-ohm link or jumper plus fuse/PTC/current limiting as appropriate.
Never connect J2 pin 1 to internal 5 V or 3.3 V rails.
Label the net clearly as VIN_12V_PROT_PASS or leave it NC.
Add supplier questions:
Can you provide the complete NVP6321 datasheet, reference schematic, layout guide, register initialization sequence, and recommended AHD input network?
Can you provide the complete CV2880 datasheet, reference schematic, PCB/BOM package, firmware/register initialization sequence, and recommended CVBS output network?
Does the CV2880 reference design require an external CVBS reconstruction filter or output buffer such as ADA4430?
What clock/crystal frequencies are required for NVP6321 and CV2880?
What rails and current limits are required for analog, digital, PLL/core, and I/O domains?
Are the parts available for production purchase, and are automotive/industrial temperature versions available?
Add validation test plan:
Verify 12 V input protection, reverse polarity behavior, TVS clamp path, and 5 V / 3.3 V / 1.8 V rails before fitting video ICs.
Test AHD 720p and 1080p camera input compatibility.
Confirm NTSC CVBS amplitude is approximately 1 Vpp into 75 ohms.
Verify color burst, sync stability, image latency, scaling behavior, and cold/hot startup.
Test with actual factory stereo/monitor input before freezing the connector pinout.
Generate a single combined export suitable to send to an electronics engineer, clearly marked “schematic shell / architecture review package — not production-ready.”

flux

I’ll create a single engineer handoff project file and downloadable Markdown export from the current docs and schematic state, clearly marked as architecture review only — not production-ready.

flux

Created the combined engineer handoff package.
Project file:
Downloadable Markdown export:
It is clearly marked “schematic shell / architecture review package — not production-ready” and includes the revised two-stage video architecture, open decisions, supplier checklist, connector pinout decision table, BOM risks, and validation plan.
Fix J2 pin 1
Create supplier email
Review BOM risks
Find scaler alternatives
Export PDF version
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Schematic

Layout

3D View

Project Specification: AHD to NTSC Inline Converter
Project Overview
Status: Draft schematic shell / architecture review.
Compact inline automotive video adapter that accepts AHD 720P/1080P camera video and generates NTSC CVBS composite video for factory stereos, monitors, and DVRs. The design currently implements the connector, automotive protection, 12V-to-5V power, 3.3V video rail, input/output video conditioning, and CVBS output driver. The AHD decoder/downscaler/CVBS encoder IC is a required missing library/datasheet item before production release.
Intended Use
Heavy-duty vehicle camera harness adapter installed inline in a waterproof/potted enclosure around 35 mm x 18 mm. Plug-and-play operation with no user controls.
Main Features
  • AHD 720P/1080P analog HD input from 4-pin vehicle/circular connector.
  • NTSC CVBS output, nominal 1 Vpp into 75 ohms.
  • 12 V automotive input with reverse-polarity and transient protection.
  • 5 V buck rail and 3.3 V low-noise video rail.
  • ESD protection on exposed video lines.
  • 4-layer PCB recommended for solid ground and video return paths.
System Architecture
AHD camera connector -> ESD/75 ohm termination/AC coupling -> AHD receiver IC -> digital BT.656 / BT.1120-style video bus -> scaler / NTSC CVBS encoder -> optional CVBS reconstruction filter/driver -> AC coupling/75 ohm output network/ESD -> output connector.
The previous one-chip missing-core assumption is superseded. The provisional receiver candidate is Nextchip NVP6321 as a placeholder block only. The provisional scaler/encoder candidate is CV2880 or equivalent as a placeholder block only. Neither should be wired at pin level until full datasheets, package data, reference circuits, rails, reset/clock/config requirements, and recommended input/output networks are available.
Power: 12V raw -> TVS -> LM74700-Q1 + N-MOSFET reverse battery protection -> MPQ4321 fixed 5V buck -> MPQ20056 3.3V LDO for video rail.
Power Tree and Budget
The current 5V and 3.3V rails are not sufficient to finalize the design. The two-stage video processor chain will likely require at least 3.3V and 1.8V rails, and may require additional core/PLL/analog rails.
Preliminary planning budget until datasheets are obtained:
  • 12V input: design protected path for at least 0.5A to 0.8A planning peak.
  • 5V rail: 0.8A to 1.0A planning peak for downstream regulator feed and any 5V loads.
  • 3.3V rail: 0.5A possible peak if AHD receiver, scaler I/O, config logic, and CVBS support share it.
  • 1.8V rail: missing; plan for 0.5A to 0.7A possible peak until IC datasheets prove otherwise.
  • Additional AVDD/PLL/DAC reference rails: TBD per selected IC datasheets.
Power-design task before layout: create final datasheet-grounded power budget and verify whether MPQ20056 250mA is sufficient. It likely is not sufficient as the only 3.3V regulator for both video ICs.
Connector Pinout
Input J1:
  1. 12V camera harness input (VIN_12V_RAW)
  2. Ground
  3. AHD video input (AHD_VIDEO_IN_RAW) 4/Shield. Cable shield/reference (SHIELD_REF)
Output J2:
  1. 5V regulated auxiliary/pass-through placeholder in current schematic; revise if output connector must pass raw 12V.
  2. Ground
  3. NTSC CVBS output (CVBS_NTSC_OUT) 4/Shield. Cable shield/reference (SHIELD_REF)
Key Components
  • U1: LM74700QDDFRQ1 ideal diode controller for reverse battery protection.
  • Q1: DMT6008LFG 60V N-MOSFET pass FET; automotive qualification must be verified or replaced.
  • D1: SMBJ24A TVS; consider SMBJ33CA per LM74700-Q1 datasheet if 24V jump-start tolerance is required.
  • U2: MPQ4321GDE-5-AEC1-Z automotive 42V 1A fixed 5V buck regulator.
  • U3: MPQ20056GG-33-AEC1-P AEC-Q100 3.3V low-noise LDO.
  • U6: ADA4430-1WYRTZ-R7 automotive video reconstruction filter/driver.
  • D2/D3: PESD5V0S1BA video ESD clamps; capacitance must be checked for AHD bandwidth.
  • AHD receiver candidate: Nextchip NVP6321 placeholder only, listed publicly as 1-channel automotive AHD receiver up to 1080p30 with BT.656 output. Requires real datasheet before schematic wiring.
  • AHD receiver backup: NVP6324 or equivalent, likely larger/multi-channel and not preferred unless NVP6321 is unavailable.
  • Scaler/encoder candidate: CV2880 placeholder only, listed publicly as digital-input scaler/analog-output video processor with BT.656/BT.1120-style support and QFP-80 12 mm x 12 mm package. Requires real datasheet/reference design before schematic wiring.
  • Encoder fallback: ADV7391/ADV7393 are available video encoder candidates but do not solve scaling by themselves; they require a separate scaler producing SD timing.
  • TP1–TP7: compact SMD test pads for VIN_12V_PROT, 5V, 3V3_VIDEO, AHD_DECODER_IN, NTSC_DAC_OUT, CVBS_NTSC_OUT, and GND.
PCB Layout Guidance
  • Use 4-layer stackup: L1 components/signals, L2 solid GND, L3 power, L4 secondary signals.
  • Keep TVS/ESD parts adjacent to connectors with short, direct return to chassis/ground reference.
  • Keep buck switch node compact and away from AHD input/CVBS output routing.
  • Route video traces as short 75 ohm controlled-impedance microstrip/stripline where practical; do not cross ground voids.
  • Put ADA4430 decoupling at VS pin and route CVBS output with continuous return plane.
  • Physically isolate power switching loop from decoder analog front end.
  • Add strain relief / mechanical anchoring in enclosure; avoid relying on solder joints for cable force.
  • Consider conformal coating or potting; verify thermal path for the buck regulator and video SoC.
Assumptions and Required Verification
  • Final AHD decoder/scaler/encoder IC and datasheet are not yet selected/imported; exact pinout, rails, clocks, reset, I2C straps, and required passives remain TBD.
  • Current schematic includes named interface nets AHD_DECODER_IN and NTSC_DAC_OUT for the missing core IC.
  • Output connector power pin is wired to 5V as a safe regulated placeholder; change to protected/raw 12V if the factory harness expects camera power pass-through.
  • SMBJ24A may clamp too low for 24V jump-start; choose TVS based on actual vehicle transient spec.
  • PESD5V0S1BA capacitance and automotive qualification must be verified for AHD 1080P bandwidth.
  • Output-side connector pinout must be verified before layout. Do not accidentally feed 5V or 3.3V into a vehicle harness. If 12V pass-through is required, make it explicit, protected, and separately labeled from internal rails.
  • ADA4430 output stage must be reviewed after the encoder is selected. Keep it only if the encoder DAC requires an external reconstruction filter/buffer. Remove or revise it if the encoder directly drives 75 ohm CVBS.
  • Add MCU, EEPROM, or configuration header only after confirming whether NVP6321/CV2880 or replacements require I2C initialization, reset timing, straps, or boot configuration.
Change Notes
  • Continued schematic completion by adding bring-up/prototype test pads TP1–TP7 on the key power and video nets.
  • Re-ran schematic review after adding test points; no open ERROR/WARNING/UNCERTAIN review checks were reported for the implemented shell.
  • Remaining blocker is still the unavailable AHD 720P/1080P decoder/downscaler/NTSC encoder IC and its datasheet-grounded support circuit.
  • Revised direction to a realistic two-stage chain: AHD receiver -> digital video bus -> scaler / NTSC CVBS encoder -> optional output filter/driver.
  • Created a separate Video Architecture Decision Record with receiver/encoder decision tables, package-fit check, preliminary power budget, and no-pin-level-wiring rule.

  • Project Overview

  • Intended Use

  • Main Features

  • System Architecture

  • Power Tree and Budget

  • Connector Pinout

  • Key Components

  • PCB Layout Guidance

  • Assumptions and Required Verification

  • Change Notes