Stereo DSP Amplifier

Thought for 10 sec

Your overall architecture is plausible, but I would challenge a few assumptions. The biggest risk areas are the INA1650 supply/headroom, ADC input biasing and level scaling, clock/reset sequencing, and TAS5825M support circuitry/layout.

1. INA1650 at 5 V single-supply: possible, but likely not ideal

The INA1650 can be used on a single supply, but powering it from only 5 V single-supply is a significant headroom compromise for a balanced audio input stage.

Main concerns

With a 5 V single supply, the INA1650 output must be biased around mid-supply, typically ~2.5 V. That leaves limited positive and negative swing before clipping. Even if the part is reasonably rail-to-rail, practical low-distortion swing will be less than the full 5 V span.

For consumer-level inputs this may be acceptable, but for balanced line-level/pro-audio signals it is probably not.

Typical signal levels:

Table

Signal level	Vrms	Vpk
2 Vrms consumer line	2.0 Vrms	2.83 Vpk
+4 dBu pro nominal	1.23 Vrms	1.74 Vpk
+18 dBu	6.15 Vrms	8.7 Vpk
+20 dBu	7.75 Vrms	11.0 Vpk
+24 dBu	12.3 Vrms	17.4 Vpk

A 5 V single-supply INA stage cannot handle high balanced input levels without attenuation before or inside the receiver path. Even 2 Vrms single-ended-equivalent signals may be close to the comfort limit depending on gain, common-mode, and output swing requirements.

Better options

I would consider one of these instead:

Option A — Keep INA1650 at 5 V, but design for consumer-level input only

Accept that the balanced input maximum level is modest. Add explicit input attenuation and document the maximum input level before clipping.

This is acceptable if your product is not expected to accept +18 dBu / +20 dBu / +24 dBu balanced sources.

Option B — Power INA1650 from a higher single supply, e.g. 9 V, 12 V, or 15 V

This gives much better headroom while avoiding a negative rail. You would then AC-couple or level-shift/attenuate into the PCM1863 ADC inputs.

This is often the best compromise.

Possible rail approach:

18 V input → low-noise 12 V or 15 V LDO/buck-LDO for INA1650
INA1650 output centered around its own mid-supply
AC-couple into PCM1863 biased at ADC common-mode

This gives the line receiver the headroom it wants while keeping the ADC safe.

Option C — Use dual analog rails for the INA1650

For best audio interface robustness, use something like ±5 V, ±9 V, ±12 V, or ±15 V for the INA1650. Then AC-couple/attenuate into the ADC.

This is electrically clean but adds power-supply complexity.

My recommendation

If this amplifier may connect to real balanced/pro-audio sources, I would not power the INA1650 from only 5 V unless you intentionally add input attenuation and accept reduced maximum input level.

A higher single analog rail, such as 12 V or 15 V, is a better default.

2. Be careful with the PCM1863 input topology

Your plan says:

INA outputs AC-coupled/RC-filtered to PCM1863 single-ended inputs

That can work, but there are several traps.

ADC input common-mode bias

The PCM1863 analog inputs generally need to sit at the ADC’s internal or external common-mode/reference point, not at ground. If you AC-couple from the INA1650, the ADC side of the coupling capacitor must be biased correctly.

Do not just AC-couple through a capacitor into a floating ADC pin.

You likely need:

Series AC coupling capacitor
Bias resistor to ADC common-mode/reference node, or use the ADC’s recommended biasing scheme
Anti-alias / RF filter resistor-capacitor network
Clamp/protection consideration if high input levels are possible

Level scaling

The INA1650 may output more voltage than the PCM1863 can accept. Check the PCM1863 full-scale input voltage for your chosen mode: single-ended vs differential, gain settings, AVDD level, and internal PGA configuration.

If the INA1650 is run from a higher rail, you almost certainly need attenuation before the ADC.

Single-ended vs differential into ADC

If the PCM1863 supports differential inputs, consider whether you actually want to preserve the differential signal path from the balanced receiver to the ADC. If using the INA1650, its purpose is to convert balanced to single-ended with high CMRR, so single-ended ADC drive is fine. But if your noise environment is severe, a fully differential ADC drive path may be preferable.

For this design, INA1650 → single-ended ADC is reasonable, but be disciplined about input scaling and biasing.

3. Missing rails / rail assumptions to verify

Your proposed rails:

Protected 18 V → TAS5825M PVDD
18 V → 3.3 V buck ≥1 A for ESP32-S3, PCM1863, TAS5825M digital
18 V → 5 V low-noise LDO for INA1650

This is close, but I would verify each IC’s rail requirements carefully.

ESP32-S3

ESP32-S3 has large transient current spikes, especially with Wi-Fi/Bluetooth active. A “≥1 A” 3.3 V buck is reasonable, but I would not size it too tightly.

Recommended:

Use a 3.3 V regulator capable of at least 1 A, preferably more if Wi-Fi is active.
Put substantial local bulk near the ESP32 module/chip:
- 10 µF to 47 µF local bulk
- Multiple 0.1 µF decouplers
If using bare ESP32-S3 rather than module, follow Espressif’s power sequencing, strapping, USB, flash, and RF layout guidance closely.

PCM1863

Check whether it needs:

AVDD
DVDD
IOVDD
Separate analog and digital decoupling
External reference/filter capacitors
Master clock / clock ratio constraints

Some audio ADCs support 3.3 V analog and 1.8/3.3 V digital I/O, but do not assume one 3.3 V rail satisfies every pin without checking.

TAS5825M

For the TAS5825M, verify whether it needs:

PVDD
DVDD / IOVDD
AVDD or internal regulator pins
GVDD/bootstrap caps, if applicable
Proper decoupling on PVDD and digital rails
Pullups for I2C
Fault/reset/mute pins
Address pin strapping
Mode pins / GPIO configuration

Do not treat it as only “PVDD + 3.3 V digital” until you have checked every power and control pin.

4. Buck noise into audio rails

A single 18 V → 3.3 V buck feeding ESP32, ADC digital, and TAS digital is efficient, but the ESP32 is noisy. The ADC and TAS digital rails may tolerate this, but you should isolate thoughtfully.

Recommended 3.3 V power tree:

Text
18 V protected
   ├── TAS5825M PVDD directly, with LC/bulk/TVS/fuse protection
   ├── 3.3 V buck
   │      ├── ESP32-S3 3.3 V branch
   │      ├── PCM1863 digital/IO branch, via ferrite or small filter
   │      ├── PCM1863 analog 3.3 V branch, preferably LDO or ferrite-filtered
   │      └── TAS5825M digital branch
   └── analog rail for INA1650

For best ADC performance, I would consider:

18 V → buck to 5 V or 3.8 V → low-noise 3.3 V LDO for PCM1863 analog
Or 3.3 V buck → ferrite bead/RC filter → PCM1863 AVDD, if performance requirements are moderate

Do not put ESP32 burst current on the exact same unfiltered local rail feeding ADC analog/reference pins.

5. Reset, mute, and sequencing traps

This is a major area to get right.

TAS5825M control pins

Make sure you include:

RESET / PDN control from ESP32 or supervisor
FAULT pin to ESP32
MUTE or shutdown control if available
Proper pullups/pulldowns so the amp stays muted/off during ESP32 boot
I2C pullups to the correct I/O voltage
Address pin configuration
Optional hardware mute button/header/test point

The amp should not wake up and drive outputs before clocks/configuration are valid.

Recommended power-up behavior

A safe sequence is usually:

18 V input stable
3.3 V stable
ESP32 boots
ADC and TAS held reset/muted
Configure clocks/I2S/I2C
Configure TAS registers
Start valid I2S stream
Unmute amplifier

And on power-down:

Mute TAS
Stop audio stream / shut down gracefully
Remove power

Use a reset supervisor if necessary. Do not rely only on ESP32 boot timing.

ESP32 boot strapping pins

If ESP32-S3 pins used for I2S, I2C, reset, or amp control overlap with strapping pins, check their required boot states. External pullups/pulldowns on TAS/ADC control lines can accidentally put the ESP32 into the wrong boot mode.

6. Clocking: decide who is master and make it deterministic

You said:

ESP32 as I2S master with BCLK/LRCLK source series resistors and separate data series resistors

This is reasonable, but check whether the PCM1863 and TAS5825M both support the exact clocking mode you intend.

Important questions

Will ESP32 generate MCLK?
Does PCM1863 require MCLK, or can it use BCLK/LRCLK only?
Does TAS5825M require MCLK, or can it operate from BCLK/LRCLK?
Are ADC and amplifier using the same sample rate family?
Can ESP32-S3 generate low-jitter enough clocks for your audio target?
Are both ADC and DAC/amp configured as I2S slaves?
Is there any asynchronous sample-rate conversion? Probably not.

Potential trap

Some audio ADCs require a stable MCLK or specific BCLK/LRCLK ratio. ESP32 I2S can generate clocks, but clock jitter may be worse than a dedicated audio oscillator/PLL solution.

For a casual/consumer DSP amp, ESP32 master may be fine.

For high audio performance, consider:

Dedicated 24.576 MHz oscillator for 48 kHz-family audio
Use an audio clock generator if needed
Keep all audio devices synchronous

Series resistors

Good idea. Place them near the driver/source.

Typical values:

BCLK: 22 Ω to 47 Ω
LRCLK: 22 Ω to 47 Ω
MCLK if used: 22 Ω to 47 Ω
SDOUT/SDIN: 22 Ω to 47 Ω, especially if traces are long

On a 150 mm board, I2S trace lengths can become nontrivial. Keep I2S routing short, referenced to solid ground, and avoid running near the class-D output filter/output nodes.

7. TAS5825M LC output filter: check values against load and TI guidance

You propose:

TAS LC filters 10 µH + 0.68 µF per BTL leg

This is in the general class-D filter range, but do not assume it is automatically correct. The ideal output filter depends on:

Speaker impedance: 4 Ω? 6 Ω? 8 Ω?
Output power
PVDD = 18 V
TAS5825M modulation scheme
Desired EMI performance
Inductor saturation current
DCR/power loss
Capacitor voltage/current/dielectric
Stability/load interaction

The LC cutoff for 10 µH and 0.68 µF is approximately:

Text
fc = 1 / (2π√(LC))
   ≈ 61 kHz

That is plausible for class-D audio filtering, but the damping/Q with the speaker load matters.

Support components often needed

For each BTL output, check TI’s recommended network:

LC output filter per half-bridge
Zobel/snubber networks if recommended
Ferrite bead option if filterless/EMI variant
Proper bootstrap or gate-drive caps if applicable
PVDD high-frequency ceramic decoupling very close to pins
Large PVDD bulk capacitance near TAS
Speaker connector ESD/EMI consideration
Output common-mode choke if needed for EMI
Do not connect speaker negative to ground; BTL outputs are both actively driven

Inductors

Use shielded power inductors with:

Saturation current above peak output current
Low DCR
Low acoustic noise
Suitable current rating at temperature
Adequate spacing from analog input/ADC circuitry

For 18 V into 4 Ω BTL, output current can be substantial. Do not use small signal inductors.

8. Protection and input power circuits not to omit

For an 18 V amplifier board, I would include:

At 18 V input

Fuse or resettable fuse
Reverse polarity protection, preferably ideal diode controller or P-channel MOSFET
TVS diode sized for your supply environment
Bulk input capacitance
EMI input filter if cable-fed
Inrush consideration if large bulk caps
Clear power connector current rating
Test points for 18 V, 3.3 V, analog rail, GND

For TAS PVDD

Local bulk electrolytic/polymer capacitance near TAS PVDD
Multiple ceramic decouplers close to PVDD pins
Star-ish/high-current routing strategy
Keep PVDD and speaker current loops away from ADC/INA

For speakers

Speaker connector rated for current
ESD/EMI treatment depending on use case
Optional overcurrent/fault reporting through TAS
Clear labeling: BTL outputs, no side grounded

9. Analog input support circuits

For the balanced input path, do not omit:

Input connector shield/chassis strategy
ESD protection on input lines
RF common-mode filtering
Input bias paths
Proper differential impedance matching
Optional input attenuation pads
AC coupling if source DC offset is possible
Protection against phantom power or miswired cables, if relevant
CMRR-preserving resistor matching

For balanced audio input, layout and impedance symmetry matter. If you add RC filters, keep them symmetrical on the + and − input lines before the INA1650.

10. Grounding and 4-layer stackup recommendation

For a 150 × 150 mm 4-layer mixed-signal class-D audio board, I would use something like:

Text
L1: Components + signals + local power
L2: Solid GND plane
L3: Power planes / routed power / some signals
L4: Signals, slower control, maybe output routing as needed

Key points:

Keep L2 as uninterrupted ground as much as possible.
Do not split ground casually.
Partition by placement and current loops rather than by cutting planes.
Keep class-D output LC filters and speaker connectors physically away from INA/ADC input section.
Place TAS close to speaker/output filter section.
Place INA/ADC close to input connectors, but away from class-D switch nodes.
Keep ESP32 RF antenna area clear if using module.
Keep I2S away from class-D output switching nodes.

11. Recommended “do not omit” list

I would make sure the schematic includes the following.

Power

Input fuse/protection
Reverse polarity protection
TVS on 18 V input
Input bulk capacitance
18 V PVDD local TAS bulk
3.3 V buck with adequate transient response
Optional filtered/LDO analog 3.3 V for ADC
Higher analog rail for INA1650 if you need real balanced-line headroom
Power-good/reset supervisor if sequencing is not guaranteed
Test points on all rails

ESP32-S3

EN/reset circuit
Boot/strap pins correctly biased
Programming interface: USB or UART/JTAG as appropriate
Adequate 3.3 V bulk
Keepout for antenna if module
Watch strapping conflict with I2S/I2C/control pins

PCM1863

Correct AVDD/DVDD/IOVDD rails
Required reference/common-mode capacitors
Proper input biasing after AC coupling
Anti-alias/RF input filters
I2C address/control pins
Reset/power-down handling if available
MCLK/BCLK/LRCLK requirements verified

TAS5825M

Correct PVDD/DVDD/IOVDD/other rails
RESET/PDN/MUTE controlled safely
FAULT routed to ESP32
I2C pullups
Address straps
Proper LC filters
PVDD decoupling close to pins
Output inductors sized for current
Speaker connector protection/labeling
Thermal copper/vias as recommended

Audio clocks

One clear clock master
Valid BCLK/LRCLK/MCLK ratios
Series resistors near source
Optional dedicated audio oscillator if performance target requires it

Bottom-line recommendation

Your architecture is workable, but I would change or scrutinize these items:

Do not default to 5 V single-supply INA1650 unless low input headroom is acceptable. For balanced/pro-audio inputs, use a higher analog rail or dual rails.
Add explicit ADC input biasing and attenuation after the INA1650. AC coupling alone is not enough.
Verify every PCM1863 and TAS5825M rail, especially analog/digital/IO/reference requirements.
Hold TAS muted/reset until clocks and I2C configuration are valid.
Consider a cleaner ADC analog supply than the raw ESP32 3.3 V buck branch.
Validate TAS LC filter values against speaker impedance, EMI target, and TI’s reference design.
Include input/output/power protection circuits early, not as layout afterthoughts.

If I had to make one major architectural adjustment, it would be:
use 18 V → 12 V or 15 V analog rail for the INA1650, then AC-couple/attenuate/bias into the PCM1863. That gives you much more robust balanced input handling without greatly complicating the rest of the system.

Worked for 5 mins 30 sec

flux

Main ICs/connectors are added. I’m now adding the support BOM: power rails/protection, ESP32 boot/debug, audio filters/pads, TAS output filters, and test points.

Worked for 29 mins 42 sec

flux

Implemented the complete schematic and BOM draft for the stereo DSP amplifier, without PCB placement or routing. Electrical ERC is clean; the remaining BOM/manufacturing issue is that generic passives, inductors, test points, and attenuation headers still need final orderable MPN/package selections before manufacturing.

Created/updated project files:

Open items:

Select final MPNs/packages for generic resistors, capacitors, inductors, test points, and jumper headers.
Verify the PCM1863DBT footprint pitch against TI’s DBT TSSOP-30 land pattern before layout.
Add final TI register configurations for PCM1863 and TAS5825M firmware.

Suggested next steps:

Finalize passive/inductor/test-point MPNs to make the BOM manufacturing-ready.
Review the schematic visually for signal-flow readability.
Set the 150 mm × 150 mm four-layer board, stackup, and placement constraints.
Start PCB placement only after you approve the schematic.

Finalize BOM and placement

Finalize passive MPNs

Verify PCM1863 footprint

Arrange schematic readability

Start PCB placement

Explain remaining risks

Files

Schematic

Layout

3D View

Stereo DSP Amplifier