EEG Signal Level Shifting
Thought for 2 mins 18 sec
You're close, but the final stage isn’t level-shifting correctly right now.
What I see
- OP5 is wired as a unity-gain follower (OUT shorted to IN1 on [Net 18](Net 18)), and its input node [Net 20](Net 20) is hard-tied to three things: the AD620 output (IC2), the upper leg of R21, and the lower leg of R20.
- R20 and R21 are both 500 Ω, forming a very stiff divider between the positive rail ([Net 21](Net 21)) and GND. This divider is loading and effectively pinning the IC2 output instead of just providing a reference.
- IC2 is tied to GND, so the AD620 output is referenced to 0 V. For single-supply conversion to an MCU ADC, the instrumentation amp’s REF should be biased to mid-rail.
What to change to get a clean 0–5 V ADC signal
- Provide a 5 V single supply to the final stage and use a rail-to-rail op-amp there (so it can swing close to 0 and 5 V).
- Create a 2.5 V mid-rail reference using a divider that is not tied directly to the signal:
- Shift the instrumentation amp output to mid-rail:
- Drive IC2 from the buffered 2.5 V Vmid (instead of GND). That centers the AD620 output around 2.5 V automatically.
- Final gain/filter stage to the Arduino:
- Reconfigure OP5 as a non-inverting amplifier for the AD620 output (now centered at 2.5 V) with the gain you need so peaks stay within 0–5 V.
- Add a simple anti-alias RC at the ADC input and keep the source impedance low enough for the ADC’s sample-and-hold to settle within the acquisition time.
Why
- Single-supply op-amp chains need mid-rail biasing; tying the signal to a stiff divider (500 Ω/500 Ω) forces the amplifier to fight the divider. The mid-rail must be generated and buffered separately, then used as a reference (especially at IC2).
- For ADCs, the bias/reference network that feeds the ADC must be low impedance so the sample-and-hold capacitor fully charges during Tacq.
A couple quick questions to size the gain and input filter correctly:
- Do you actually have a 5 V rail available on this board (or from the Arduino) to power the final stage?
- Which Arduino/ADC reference are you using (5 V default or an external ref), and what sampling rate?
- What amplitude do you currently see at IC2 after the earlier gain stages (approximate peak-to-peak)?
Confirm 5V and ADC ref
Ask how to bias REF
Provide signal amplitude
Request op-amp selection
Set divider values
