I’ll add the remaining input/output protection parts, replace the backplane and CAN termination placeholders with closer exact parts if available, update the power/CAN docs, then rerun ERC.
Project Specification — Open Modular UNO-Q PLC Rev B
Status: Design decisions locked; verification and capture in progress
Revision: Rev B
Primary architecture: Open Modular UNO-Q PLC
Explicit scope note: This project is for the Open Modular UNO-Q PLC Rev B architecture only. It is not the USB-C Wi-Fi/BLE environmental sensor project.
1. Project Overview
Design and build an open, DIN-rail-mounted, modular PLC system based around the Arduino UNO Q. The system uses the UNO Q as the CPU/HMI/edge-compute controller and uses CAN bus for modular I/O expansion.
The architecture is original and open. It is not intended to clone Allen-Bradley, Siemens, or any other vendor, though it intentionally uses common industrial control design patterns.
Current Rev B status: the core design decisions are locked. Remaining work is verification, KiCad capture, bench validation, firmware preparation, and first-board bring-up.
2. Intended Use
Target applications include:
Plumbing pump panels
Float switch control
Greenhouse automation
Mushroom grow rooms
Irrigation control
Aircrete/geopolymer process skids
Small test stands
Pneumatic machines
Heating/cooling experiments
VFD control
Sensor logging
Shop automation
Training ladder logic
This system is not a certified safety PLC and is not a direct replacement for industrial safety systems.
3. What the System Should Do
Run OpenPLC / IEC-style ladder logic control.
Maintain a PLC-style process image table.
Communicate with modular I/O nodes over CAN.
Provide protected 24 VDC digital outputs.
Read opto-isolated 12/24 V digital inputs.
Support relay outputs for dry-contact and heavier interface commands.
Support protected analog input and output modules.
Provide web dashboard, configuration, logging, alarm history, and service access through the UNO Q Linux side.
Keep real-time I/O scan and output control under the UNO Q STM32 real-time side.
Fail outputs OFF unless CPU and module watchdogs are healthy.
4. Main Features
Arduino UNO Q CPU / HMI / edge-compute controller
OpenPLC runtime and management layer
CAN-based modular I/O expansion
Local microcontroller on each I/O module
24 VDC field power distribution
Opto-isolated digital inputs
Smart high-side protected outputs
Mechanical relay outputs with dry contacts
Protected 0–10 V / 4–20 mA analog inputs
Protected 0–10 V analog outputs
Per-channel LEDs and module fault/status LEDs
Removable screw terminals
Module ID / address setting
Watchdog and failsafe behavior
3D-printed DIN-rail housings
KiCad as the production PCB design tool
Fritzing only for wiring diagrams and educational documentation
5. System Architecture
The PLC is modular rather than one large Arduino shield.
Diagram
Each I/O module includes:
Local microcontroller
CAN transceiver
24 V power input from the backplane
Field-side protection
Per-channel LEDs
Removable screw terminals
Module ID / address setting
Watchdog/failsafe behavior
6. Hardware Subsystems
6.1 CPU / Power Module
Core features:
Arduino UNO Q
24 VDC power input
Main fuse
Reverse-polarity protection
TVS surge protection
EMI filtering
5 V regulator for UNO Q
CAN transceiver
RS-485 transceiver
Watchdog relay or watchdog output
Service USB-C access
System status LEDs
DIN-rail housing
Locked Rev B CPU/power direction:
CPU module: OMUPLC-CPU-POWER-UNOQ-RevB.
24 V input protection: FDD5614P reverse-polarity MOSFET, SMBJ33A TVS, Littelfuse 8 A protection.
5 V CPU rail: TPS54360B 3.5 A buck plus 1812L300 PTC.
UNO Q 5 V input path uses the confirmed UNO Q 5 V header/power input approach from the Rev B schematic-entry notes.
The CPU module must not feed dirty panel power directly into the UNO Q without protection.
6.2 16DI Opto-Isolated Digital Input Module
Purpose:
Float switches
Limit switches
Pushbuttons
Pressure switches
Proximity sensors
Leak sensors
Door switches
Selector switches
Each channel field path:
Text
INx terminal -> current-limiting resistor -> RC filter -> opto-isolator LED -> COM terminal
Each channel logic path:
Text
3.3 V pullup -> local MCU input -> opto transistor to logic ground
Features:
16 opto-isolated 12/24 V digital inputs
Per-channel status LED
Hardware filtering
Software debounce
Input inversion setting
Common terminal grouping
CAN status reporting
Rev B proof-of-concept uses the 4DI portion of the combo module before expanding to full 16DI.
6.3 8DO Smart High-Side Output Module
Purpose:
24 VDC solenoid valves
Pneumatic valve manifolds
Relay coils
Small contactor coils
Indicator lamps
Buzzers
Small DC loads within rating
Output wiring:
Text
24 V FIELD+ -> smart high-side switch -> OUTx terminal -> load -> 0 V COM
Features:
8 protected sourcing outputs
Smart high-side switch ICs
Short-circuit protection
Overcurrent protection
Thermal shutdown
Inductive load protection
Open-load or current-sense diagnostics where available
Per-channel LED
Fault LED
Output bank fuse
Watchdog-controlled output enable
Default behavior:
No firmware: outputs OFF
Booting: outputs OFF
CAN timeout: outputs OFF
Watchdog expired: outputs OFF
Overcurrent: affected channel OFF plus fault
Output power lost: fault reported
Rev B proof-of-concept uses the 4DO-HS portion of the combo module before expanding to full 8DO-HS.
6.4 8RLY Relay Output Module
Purpose:
Dry contacts
AC control circuits
VFD run/stop inputs
Thermostat-style contacts
Contactor commands
Odd-voltage equipment interfaces
Heavier I/O interfacing through external contactors or starters
Each relay channel:
Text
local MCU output -> driver transistor or relay driver IC -> 24 V relay coil -> flyback diode or TVS
Contact side:
COM
NO
NC
Recommended design:
8 mechanical relays
24 VDC relay coils
COM / NO / NC terminals where space allows
Isolation slots between coil/logic and contact side
MOV or snubber footprints for inductive loads
Per-relay LED
Replaceable relay module option if possible
Important rule: onboard relays should command contactors, starters, SSRs, or VFDs for heavy loads. They should not directly switch large pumps, compressors, heaters, or motors.
6.5 4AI Analog Input Module
Purpose:
Pressure transmitters
Tank level sensors
Flow transmitters
Temperature transmitters
VFD feedback
Current sensors
Each channel selectable:
0–10 V mode
4–20 mA mode
4–20 mA conversion uses a 150 ohm precision resistor:
Table
Current
Sense Voltage
4 mA
0.6 V
20 mA
3.0 V
Features:
4 protected analog inputs
0–10 V / 4–20 mA mode selection
Input TVS protection
RC filtering
Precision shunt resistors
Dedicated ADC preferred
Calibration values stored in module memory
Broken-wire detection for 4–20 mA where possible
6.6 4AO Analog Output Module
Purpose:
VFD speed reference
Proportional valve control
Damper actuator control
Setpoint output
0–10 V process control
Architecture:
Text
local MCU -> DAC -> op-amp gain stage -> protected 0–10 V output
Features:
4 analog outputs
0–10 V range
Protected outputs
Calibration constants
Output disable on watchdog fault
Optional manual override in later revision
7. Interfaces and Connections
CAN Bus Backplane Connector
Minimum bus connector pinout:
Table
Pin
Signal
1
+24 V FIELD
2
0 V FIELD
3
CANH
4
CANL
5
SHIELD / CHASSIS
6
MODULE_PRESENT
7
SYNC / IRQ
8
RESERVED
Locked Rev B interface decisions:
Initial CAN bitrate: 250 kbit/s.
Later CAN bitrate target after signal-integrity verification: 500 kbit/s.
Backplane connector family: Phoenix MC 1,5/10-G-3,81.
Field terminals: Phoenix MKDS family.
DO terminals: Phoenix MSTBA family.
CAN is preferred over raw GPIO or I2C because it is noise tolerant, supports multiple nodes, includes arbitration, is common in industrial/vehicle systems, works over short DIN-rail module distances, and allows smart addressable modules.
Each module should include:
CAN transceiver
Termination jumper
Address DIP switches or rotary switch
Module type ID
Firmware version register
Watchdog timeout
Fault reporting
First implementation may use short jumper cables between modules. Later versions may use a passive DIN-rail backplane PCB.
Service / External Interfaces
USB-C service access on the UNO Q module
Wi-Fi / network access through UNO Q
RS-485 transceiver on CPU module
Removable field screw terminals on I/O modules
Chassis/shield connection on backplane
8. Power and Runtime Expectations
Primary system input is 24 VDC panel/field power. The system is expected to run from industrial 24 VDC supplies rather than battery power.
Key expectations:
CPU module accepts protected 24 VDC input.
+24 V FIELD BUS is distributed to modules.
Buck converter generates 5 V BOARD / UNO Q supply.
Output modules switch and protect 24 V field loads.
Safety relay / contactor should remove output power from smart-output and relay-coil banks during safety stop.
9. Power Tree and Power Budget
Power tree:
Diagram
Locked Rev B power budget/protection direction:
Combo module 5 V buck: LM5164, 1 A class design.
CPU module 5 V buck: TPS54360B, 3.5 A class design.
24 V input protection and 5 V rail protection are already defined in the Rev B locked design package.
Detailed per-module current and thermal checks remain part of verification, not architecture selection.
10. Process Image Model
The CPU maintains:
Text
Digital Inputs: DI[0..255]
Digital Outputs: DO[0..255]
Relay Outputs: RLY[0..127]
Analog Inputs: AI[0..63]
Analog Outputs: AO[0..63]
Faults: MODULE_FAULT[], CHANNEL_FAULT[], WATCHDOG_FAULT[], OVERCURRENT[], OPEN_LOAD[], OVERTEMP[]
PLC scan cycle:
Poll input modules
Update input image table
Run OpenPLC logic
Update output image table
Send output commands to modules
Read diagnostics and faults
Log events
Repeat
Outputs default OFF unless CPU and module watchdogs are healthy.
11. Firmware-Relevant Hardware Requirements
UNO Q Responsibility Split
Linux side:
OpenPLC runtime / management layer
Dashboard
Data logging
Alarm history
Configuration files
MQTT / network services
Camera / AI / advanced diagnostics later
STM32 real-time side:
PLC scan loop
CAN module polling
I/O update
Watchdog
Failsafe output control
Timing-critical logic
The Linux side should not directly drive output pins. The real-time MCU side should own actual I/O scan and output state.
Read TI TPS274160B register section; extract CPOL/CPHA, output command register, CS/diagnostic register format for firmware.
5
Reverse-polarity bench verification
Pre-fab bench test
Breadboard AO3401A + BZX84-C10 on 24 V bench supply; verify gate clamping under forward and reverse polarity before PCB fab.
6
TPS274160B thermal verification
Post-build bench test
Run 0.5 A/channel continuous in closed 3D-printed enclosure; measure exposed-pad temperature rise after first board is assembled.
21. Assumptions
Primary field/control supply is nominal 24 VDC.
UNO Q is the selected CPU platform.
Initial hardware is prototype/validation intent, not certified industrial product.
CAN bus distances are short within DIN-rail module assemblies for Rev B.
Locked design decisions may only change if a verification task identifies a concrete electrical, thermal, mechanical, availability, or safety issue.
22. Change Notes
Created initial Rev B project specification from the supplied Open Modular UNO-Q PLC Design Proposal.
Explicitly scoped the project to the Open Modular UNO-Q PLC Rev B architecture and excluded the unrelated USB-C environmental sensor project.
Updated Rev B status from open architecture exploration to locked design decisions with six remaining verification/capture tasks.
Added locked connector, CAN bitrate, power/protection, module-build, KiCad capture, stackup, and first-article mechanical targets from the project status bridge.