Access Reader Design
Worked for 1 min 27 sec
Текущий 80×100 мм layout всё ещё физически перегружен и даже однослойный targeted router блокируется; для order-ready в пределах вашего лимита увеличиваю плату до 120×100 мм и повторяю edge-placement/stackup.
Thought for 12 sec
В этом запуске я успел перечитать live layout/DRC/stackup: плата сейчас 80×100 мм, сильно перегружена, часть компонентов/отверстий выходит за габарит, DRC всё ещё показывает сотни airwires, а stackup readback остаётся некорректным — фактически внутренние GND/PWR слои не подтверждены как рабочие.
Что осталось сделать:
- Пополнить ACUs — сейчас AI-функции недоступны, поэтому я не могу продолжать tool execution.
- Увеличить плату до 120×100 мм в пределах вашего лимита.
- Повторить placement: все разъёмы/клеммники на кромки наружу, 4 отверстия Ø3.2 по углам, antenna keepout у края.
- Исправить/подтвердить stackup Top / Inner1 GND / Inner2 PWR / Bottom.
- Завершить routing, убрать все airwires, пройти DRC.
- Только после чистого DRC экспортировать order-ready Gerber+drill, BOM с DNP-колонками и Pick-and-Place.
Текущий пакет не order-ready.
Продолжить после ACUs
Чеклист DRC проблем
Проверить DNP BOM
Проверить разъёмы
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Access Reader Full Prototype Ready-to-Export Checklist
Status
Created 2026-07-09 after critical correction. This is the execution gate to use when live schematic/layout tools regain project context.
Prototype Definition
First Rev A prototype is a single fully populated board:
- 802.3af PoE path populated: RJ45 MagJack, AG9905-MTB, W5500 Ethernet.
- 9-32 V DC path populated: DC input protection and LMR16020 5 V buck.
- Wi-Fi/BLE populated: ESP32-S3-WROOM-1-N16R2.
5V_POE_PRE_ORand5V_DC_PRE_ORare not directly tied; both enter reverse-blocking OR-ing / priority mux and only then become5V_SYS.- Board size target: 80 × 100 mm preferred. Growth is allowed only if needed for antenna/keepout/mounting clearance; hard maximum 120 × 100 mm.
- RFID antennas are part of Rev A now, not deferred to EVT: on-board 13.56 MHz PCB loop plus external 125 kHz coil connector and tuning placeholders.
Schematic Gate
Table
| Check | Pass Criteria |
|---|---|
| PoE branch | RJ45/MagJack and AG9905-MTB present, populated, not DNP, output named 5V_POE_PRE_OR. |
| DC branch | 9-32 V input, fuse/TVS/reverse protection and LMR16020 support circuit present, populated, output named 5V_DC_PRE_OR. |
| OR-ing | Both 5 V sources feed reverse-blocking ideal-diode OR or power mux; common output is 5V_SYS. |
| No direct parallel | ERC/netlist confirms no direct short between 5V_POE_PRE_OR and 5V_DC_PRE_OR. |
| 3.3 V rail | 3.3 V buck input from 5V_SYS, output 3V3_SYS, rated for 2 A class. |
| Ethernet | W5500 populated, SPI shared with CLRC663, separate CS/INT/RST nets. |
| Wi-Fi | ESP32-S3 antenna keepout called out and Wi-Fi remains populated. |
| Boot safety | GPIO0/GPIO3/GPIO45/GPIO46 external circuits do not force bad boot states. |
| Test points | Add TP for DC input, 5V_POE_PRE_OR, 5V_DC_PRE_OR, 5V_SYS, 3V3_SYS, GND, ESP_EN, BOOT_IO0, SPI, I2C, RS-485. |
BOM Population Gate
Table
| Group | Required Prototype Status |
|---|---|
| AG9905-MTB PoE module and PoE support/protection | Populate |
| RJ45 MagJack / Ethernet connector | Populate |
| W5500 and W5500 crystal/decoupling/support | Populate |
| LMR16020 and buck inductor/diode/feedback/input/output caps | Populate |
| OR-ing / power mux / ideal-diode FETs and support passives | Populate |
| ESP32-S3-WROOM-1-N16R2 and boot/reset/USB support | Populate |
| 5 V to 3.3 V buck and support components | Populate |
| CLRC663 NFC and tune/test placeholders | Populate, except intentionally tune-option parts |
| EM4095 LF and tune/test placeholders | Populate, except intentionally tune-option parts |
| GM861 QR connector/power switch | Populate |
| RS-485, Wiegand, inputs, tamper, relays, RTC, UI | Populate |
Mechanical and RFID Antenna Gate
Table
| Check | Pass Criteria |
|---|---|
| Board envelope | 80 × 100 mm preferred; if enlarged, justify the reason and keep within 120 × 100 mm absolute maximum. |
| Connector edge access | All cable connectors and terminal blocks are placed on board edges with mating/opening/cable-entry side facing outward and with unobstructed plug/cable insertion volume outside the board outline. Inward or mid-board access is a reject condition. |
| Required edge connectors | RJ45/MagJack Ethernet, 9–32 V DC input, both relay NO/NC/COM terminal blocks, service USB, RS-485, Wiegand, two input connectors, GM861 QR connector/FPC/header and J101 125 kHz coil connector are all edge-mounted and outward-facing. |
| RJ45 access | RJ45 is specifically verified on a PCB edge, not in the board center, with room for a plug/boot and no obstruction by mounting holes, tall parts or adjacent connectors. |
| Mounting holes | H1–H4 present as four M3 / Ø3.2 mm mounting holes at board corners, ~5 mm center inset from edges. |
| Mounting keepout | ≥6 mm copper/component keepout around each mounting hole; confirm in PCB layout and CAM/Gerber viewer. |
| 13.56 MHz antenna | U8 present as ~40 × 40 mm printed PCB loop antenna connected through CLRC663 matching placeholders. Requested ANT1 designator was unavailable, so Flux assigned U8. |
| NFC matching/EMC | R101/R102/C101/C102/C103/C104 present as CLRC663 Rq/Cs/Cp/EMC tuning placeholders; tune/DNP at EVT after measuring antenna. |
| NFC all-layer keepout | No copper, planes, traces, stitching vias or components under the NFC loop on any copper layer. |
| 125 kHz coil interface | J101 present as 2-pin connector for external EM4095 coil; C111 and C112 present as resonant/FCAP tuning placeholders. |
| LF reserved zone | Reserved keepout/clearance zone next to J101 for external coil approach and wiring; no noisy power/Ethernet/relay circuitry in this zone. |
| RF floorplan | NFC/LF presentation zone is at a board edge and away from LMR16020, AG9905/PoE flyback, relays, W5500/RJ45 and ESP32 antenna. |
| EVT note | Exact NFC/LF tuning values are EVT tasks; do not treat DNP placeholders as final production values. |
pcbfast Fabrication Parameters
- Recommended layers: 4-layer. Acceptable planning range: 2-4 layers, but 4-layer is preferred for Ethernet/USB/SPI/Wi-Fi and power integrity.
- Stackup: Top signal/components, Inner1 solid GND, Inner2 power, Bottom signal.
- Minimum trace/space: 6 mil / 6 mil.
- Minimum drill: 0.3 mm.
- Surface finish: ENIG.
- Use wide copper for
5V_SYS, source 5 V paths and relay/LED loads; use stitching vias for GND returns. - Confirm finished board outline is compact and never larger than 120 × 100 mm.
Placement Gate
- H1–H4 at four corners with ~5 mm edge inset and ≥6 mm keepout.
- Hard connector rule: every connector/terminal block must be on a board edge, facing outward, with clear external insertion volume; inconvenient cable access is a manufacturing defect.
- Required edge/outward-facing connectors: RJ45/MagJack, 9–32 V DC input, both relay NO/NC/COM terminal blocks, service USB, RS-485, Wiegand, two input connectors, GM861 QR connector/FPC/header and J101.
- Connector insertion keepouts must not overlap components, mounting-hole keepouts, screw access, neighboring connectors, antenna keepouts or board outline constraints.
- U8 13.56 MHz printed loop at the card presentation edge with all-layer copper/component keepout underneath.
- J101 125 kHz external coil connector adjacent to the same presentation zone; C111/C112 nearby.
- R101/R102/C101–C104 between U13 and U8 with short symmetric antenna path.
- ESP32 module at board edge with antenna facing outward and all-layer antenna keepout.
- RJ45/MagJack on board edge, mechanically accessible.
- RJ45/MagJack must not be mid-board; jack opening faces off-board with clearance for the Ethernet plug and boot.
- AG9905-MTB near RJ45/PoE path while respecting isolation/thermal rules.
- LMR16020 buck near DC input, with compact hot loop and SW node kept away from RF/ESP32 antenna.
- OR-ing/mux close to the merge point between AG9905 5 V and LMR16020 5 V outputs.
- CLRC663/NFC and EM4095/LF antenna zones away from PoE, DC/DC inductors and relay coils.
- USB service connector on edge with short D+/D- route to ESP32.
Routing Gate
- Route power first: source paths, OR-ing,
5V_SYS,3V3_SYS, relay/LED loads. - Route USB D+/D- as a short differential pair with continuous GND reference.
- Route Ethernet pairs from RJ45/MagJack to W5500 with matched pair treatment and continuous reference.
- Route shared SPI with short stubs and clean chip-select separation.
- Keep switching-node copper compact; keep feedback traces away from inductor/SW node.
- Add GND stitching near high-speed via transitions and around board perimeter where useful.
DRC/ERC Export Gate
Block export until:
- No airwires.
- No missing footprints.
- No invalid layers.
- No cross-net overlapping copper.
- Connector edge-access review passes for RJ45, DC input, relay terminals, USB, RS-485, Wiegand, inputs, GM861 and J101; any connector that cannot be physically plugged in is a blocker.
- H1–H4 hole sizes/locations and keepouts are verified in layout.
- U8/J101 antenna presentation zone and all-layer NFC copper keepout are verified in layout and CAM/Gerber viewer.
- No critical ERC power-pin/floating/single-pin-net errors unless explicitly justified.
- Gerbers visually checked in CAM viewer.
- BOM and pick-and-place checked for all populated PoE, DC and Ethernet/Wi-Fi components.
Current Execution Note — 2026-07-09
- Schematic update completed for antennas and mounting components: H1–H4, U8, R101/R102, C101–C104, J101, C111/C112.
- Layout placement, board outline mutation and keepout primitive creation still require confirmation because PCB layout tools returned missing project-context errors during this pass.
Export Package Required
- Gerber ZIP including drill files.
- BOM CSV with all populated Rev A prototype components.
- Pick-and-place CSV.
- Optional IPC-D-356/netlist for electrical test.
- Optional STEP/GLB for mechanical review.
Status
Prototype Definition
Schematic Gate
BOM Population Gate
Mechanical and RFID Antenna Gate
pcbfast Fabrication Parameters
Placement Gate
Routing Gate
DRC/ERC Export Gate
Current Execution Note — 2026-07-09
Export Package Required
