Access Reader Design
Worked for 1 min 27 sec
Текущий 80×100 мм layout всё ещё физически перегружен и даже однослойный targeted router блокируется; для order-ready в пределах вашего лимита увеличиваю плату до 120×100 мм и повторяю edge-placement/stackup.
Thought for 12 sec
В этом запуске я успел перечитать live layout/DRC/stackup: плата сейчас 80×100 мм, сильно перегружена, часть компонентов/отверстий выходит за габарит, DRC всё ещё показывает сотни airwires, а stackup readback остаётся некорректным — фактически внутренние GND/PWR слои не подтверждены как рабочие.
Что осталось сделать:
- Пополнить ACUs — сейчас AI-функции недоступны, поэтому я не могу продолжать tool execution.
- Увеличить плату до 120×100 мм в пределах вашего лимита.
- Повторить placement: все разъёмы/клеммники на кромки наружу, 4 отверстия Ø3.2 по углам, antenna keepout у края.
- Исправить/подтвердить stackup Top / Inner1 GND / Inner2 PWR / Bottom.
- Завершить routing, убрать все airwires, пройти DRC.
- Только после чистого DRC экспортировать order-ready Gerber+drill, BOM с DNP-колонками и Pick-and-Place.
Текущий пакет не order-ready.
Продолжить после ACUs
Чеклист DRC проблем
Проверить DNP BOM
Проверить разъёмы
Сохранить требования
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Access Reader GPIO Map and Population Matrix
Status
Updated 2026-07-09 after critical prototype correction: first Rev A prototype is one fully populated board with both power inputs and both network paths.
Critical MCU Decision
- MCU: ESP32-S3-WROOM-1-N16R2.
- Do not use ESP32-S3-WROOM-1-N16R8: octal PSRAM occupies GPIO35-GPIO37.
- External W25Q128 is not used; N16R2 includes 16 MB flash.
ESP32-S3 GPIO Allocation
Table
| Function | ESP32-S3 GPIO | Net / Peripheral | Notes |
|---|---|---|---|
| SPI SCK | GPIO12 | SPI_SCK | Shared CLRC663 + W5500 |
| SPI MOSI | GPIO11 | SPI_MOSI | Shared CLRC663 + W5500 |
| SPI MISO | GPIO13 | SPI_MISO | Shared CLRC663 + W5500; verify tri-state on both slaves |
| CLRC663 CS | GPIO10 | CLRC663_CS | U13 IF3/NSS |
| CLRC663 IRQ | GPIO14 | CLRC663_IRQ | Interrupt input to MCU |
| CLRC663 PDOWN | GPIO9 | CLRC663_PDOWN | Power-down/reset control |
| W5500 CS | GPIO21 | W5500_CS | Populate in prototype |
| W5500 INT | GPIO47 | W5500_INT | Populate in prototype |
| W5500 RST | GPIO48 | W5500_RST | Populate in prototype |
| GM861 UART TX | GPIO17 | QR_RXD_TO_MODULE | MCU TX to scanner RXD |
| GM861 UART RX | GPIO18 | QR_TXD_FROM_MODULE | Scanner TXD to MCU RX |
| GM861 TRIG | GPIO8 | QR_TRIG | Scanner trigger |
| GM861 PWR_EN | GPIO15 | QR_PWR_EN | P-MOS high-side power switch gate, active-low behavior to verify in firmware |
| EM4095 SHD | GPIO16 | EM4095_SHD | SHD high = sleep per datasheet |
| EM4095 MOD | GPIO7 | EM4095_MOD | Modulation control |
| EM4095 DEMOD | GPIO6 | EM4095_DEMOD | RMT input |
| RS-485 TX | GPIO41 | RS485_TX | UART2 TX to MAX3485 DI |
| RS-485 RX | GPIO42 | RS485_RX | UART2 RX from MAX3485 RO |
| RS-485 DE/~RE | GPIO40 | RS485_DE | Direction control, default receive in firmware |
| Wiegand D0 | GPIO39 | WIEGAND_D0_DRV | Open-drain output driver |
| Wiegand D1 | GPIO38 | WIEGAND_D1_DRV | Open-drain output driver |
| Relay K1 | GPIO4 | RELAY_K1_DRV | Low-side MOSFET driver |
| Relay K2 | GPIO5 | RELAY_K2_DRV | Low-side MOSFET driver |
| Input IN1 | GPIO1 | IN1_GPIO | Opto output with pull-up |
| Input IN2 | GPIO2 | IN2_GPIO | Opto output with pull-up |
| I2C SDA | GPIO35 | I2C_SDA | PCF8563 + optional ATECC608B |
| I2C SCL | GPIO36 | I2C_SCL | PCF8563 + optional ATECC608B |
| Tamper | GPIO46 | TAMPER_GPIO | Strapping-sensitive; keep external circuit boot-safe |
| Buzzer | GPIO45 | BUZZER_DRV | Strapping-sensitive; pulldown/default-off required |
| WS2812B | GPIO3 | WS2812_DIN | Strapping-sensitive; avoid hard pull at reset |
| USB D- | GPIO19 | USB_DN | ESP32-S3 native USB-Serial-JTAG |
| USB D+ | GPIO20 | USB_DP | ESP32-S3 native USB-Serial-JTAG |
| UART0 TX | GPIO43 / TXD0 | UART0_TX | Service/debug header |
| UART0 RX | GPIO44 / RXD0 | UART0_RX | Service/debug header |
| BOOT | GPIO0 | BOOT_IO0 | Pull-up + BOOT button |
| EN/RESET | EN | ESP_EN | Pull-up + RC reset |
Rev A Prototype Population Matrix
Table
| Block | First Rev A Prototype Population | Notes |
|---|---|---|
| DC input terminal + 9-32 V buck using LMR16020 | Populate | Produces 5V_DC_PRE_OR |
| AG9905-MTB IEEE 802.3af PoE 5 V module path | Populate | Produces 5V_POE_PRE_OR |
| 5 V source OR-ing stage | Populate | Reverse-blocking ideal-diode OR / priority power mux; output net 5V_SYS |
| W5500 Ethernet controller | Populate | Shares SPI with CLRC663; separate CS/INT/RST |
| RJ45 MagJack / PoE-capable Ethernet connector | Populate | Ethernet + PoE path both present |
| ESP32-S3-WROOM-1-N16R2 Wi-Fi/BLE | Populate | Wi-Fi retained even with Ethernet populated |
| 5 V to 3.3 V buck | Populate | Feeds 3V3_SYS logic/RF |
| CLRC663 + 13.56 MHz matching placeholders | Populate | Matching values may remain tune/DNP placeholders only where intentionally marked as RF options |
| EM4095 + 125 kHz antenna/tuning placeholders | Populate | Tune parts may remain RF option placeholders |
| GM861 connector + QR power switch | Populate | Verify exact harness/FPC orientation before power |
| RS-485, Wiegand output, two opto inputs, tamper | Populate | External-port protection required |
| PCF8563 + CR1220 | Populate | I2C on GPIO35/GPIO36 |
| ATECC608B secure element | Populate if available / allowed optional | Optional security feature, not part of PoE/Ethernet DNP decision |
| Relays K1/K2 dry contacts | Populate | Dry contacts only |
Power Merge Requirement
5V_POE_PRE_ORand5V_DC_PRE_ORmust not be directly connected together.- Both sources feed a reverse-blocking OR-ing/power-mux stage.
- The common downstream rail is
5V_SYS, then3V3_SYSvia the 3.3 V buck. - No current sharing between PoE and DC is assumed; if priority is required, implement it in the OR-ing/power-mux stage.
Known Review Risks
- GPIO3, GPIO45 and GPIO46 are strapping-sensitive and must remain boot-safe.
- Shared SPI MISO tri-state behavior of CLRC663 and W5500 must be confirmed in firmware/hardware test.
- PoE power margin may require firmware power limiting of RF, QR, LEDs and relays.
- GM861 connector pinout has variant/orientation risk; verify the exact FPC/harness before applying power.
- NFC/LF antenna tuning is EVT work; keep matching/tuning option footprints and test pads.
Status
Critical MCU Decision
ESP32-S3 GPIO Allocation
Rev A Prototype Population Matrix
Power Merge Requirement
Known Review Risks
