Project Assistance Inquiry
1:07
Below is the proposed wiring plan for your zero crossing detection stage using the LM393 Comparator with the ZMPT101B_Module:
Wiring Plan
Table
| Component/Node | Connection | Notes |
|---|---|---|
| [ZMPT101B_Module] | VCC → V1 output (5 V) | Ensure the module is powered using the regulated DC supply. |
| GND → Ground | All grounds must be common. | |
| OUT → LM393 non-inverting input | The "OUT" pin of the sensor is fed to the comparator. | |
| [LM393 Comparator] (U1) | Pin 8 (VCC) → V1 output | Use the 5 V supply from the DC supply. |
| Pin 4 (GND) → Ground | Connect to the common ground. | |
| Pin 3 (1IN+) ← Connected to [ZMPT101B_Module] OUT | Receives the AC sensor output. | |
| Pin 2 (1IN-) ← Voltage divider output | See voltage divider section below. | |
| Pin 1 (1OUT) → Pull-up resistor output | Use a pull-up resistor (see below) since the LM393 output is open collector. | |
| Voltage Divider for Reference (for Pin 2) | R1 from V1 to LM393 Pin 2 | Example value: 10 kΩ. This resistor pulls the reference up from the supply. |
| R2 from LM393 Pin 2 to Ground | Example value: 10 kΩ. Together with R1, it sets a mid-supply reference (~2.5 V) for zero crossing. | |
| Comparator Output Pull-Up | R3 from LM393 Pin 1 to V1 output | Example value: 10 kΩ. This resistor pulls the LM393 output high when the open collector is inactive. |
Additional Notes:
-
Signal Conditioning:
The AC signal from the ZMPT101B_Module may need filtering or AC coupling. Ensure that any DC offsets are removed as needed before reaching the comparator's non-inverting input. -
Comparator Operation:
When the AC sensor’s output (after conditioning) rises above the 2.5 V reference, the comparator will switch its output. The resulting digital signal (with the help of the pull-up resistor R3) can then be used to trigger your subsequent PLL stage for synchronization.
Would you like additional details on any part of the wiring (for example, refining the voltage divider values), or help with next connections such as interfacing the comparator output with a PLL?
Refining Divider Values
PLL Stage Design
Comparator Output Conditioning
414 days
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