SNSPD PCB Slot

flux

PCB Release Notes — Current Revision
Project: Cryogenic DC-Coupled SNSPD Readout
Status: Engineering prototype; not approved for production or cryostat installation
Current design
  • PCB: 48 × 30 mm, four layers
  • Primary ground reference: solid L2 GND plane
  • SNSPD: centered 6 × 6 mm, two-terminal placeholder
    • Top-left pad: SIGNAL → VIN
    • Bottom-right pad: RETURN → GND
    • 7 × 7 mm die-attach area
    • Top illumination required
  • Bias path: J1 → R5 (100 kΩ) → L1 (4.7 µH) → VIN
  • Input network: AC-coupling capacitor into the OPA855 input and R4 = 50 Ω termination
  • Amplifier: OPA855
  • Feedback: R1 = 453 Ω, R2 = 75 Ω
    • Nominal closed-loop gain: 7.04 V/V
    • Equivalent gain: 16.95 dB
  • Output: VOUT → J2, with R3 = 200 Ω to GND
  • Supply inputs: J3 = positive rail, J4 = negative rail
  • Current intended operating rails: +2.5 V and −2.5 V
  • RF traces: VIN and VOUT, nominally 0.180 mm on L1, referenced to L2 GND
  • Latest reported routing status: zero airwires, dangling traces, and active ERC/DRC errors
Important hold points
  1. OPA855 decoupling is unresolved.
    The previous supply capacitors were removed. Exact local bypass requirements must be verified directly from the OPA855 device datasheet before release. A multi-GHz amplifier should not be fabricated without an approved supply-decoupling implementation.
  2. Stackup is provisional.
    The current “PCBWay Custom” stackup is not an approved PCB Power India stackup. Obtain:
    • exact four-layer construction
    • finished copper thicknesses
    • L1–L2 dielectric thickness and Dk
    • recommended L1 width for 50 Ω
    • impedance tolerance and coupon/test availability
  3. SNSPD footprint remains provisional.
    Confirm:
    • real die dimensions and thickness
    • exact bond-pad coordinates and metallurgy
    • signal and return pad locations
    • backside electrical requirements
    • approved die-attach material
  4. Wire-bond finish is unresolved.
    The PCB pads are exposed top-copper lands with solder paste suppressed. Select ENIG, ENEPIG, or soft gold only after agreement between the SNSPD supplier, bonding laboratory, and PCB Power.
  5. OptiCool mechanics remain provisional.
    • Board fits the nominal pod envelope in 2D.
    • Mounting-hole coordinates are not verified.
    • RF/DC feedthrough mating geometry and cable clearance are not confirmed.
    • Do not add or drill mounting holes from assumed dimensions.
  6. Cryogenic qualification is not established.
    • OPA855 operation on this exact PCB at 4 K is unverified.
    • L1 inductance, Q, self-resonance, and DC resistance at 4 K are unverified.
    • Connector, laminate, solder, adhesive, and capacitor behavior at 4 K require validation.
    • Results from the referenced paper do not automatically qualify this exact BOM or thermal arrangement.
Simulation status
  • Behavioral U1 transient:
    • J1 = 1.5 V
    • nominal bias = 15 µA
    • switching threshold = 20 µA
    • J3/J4 = ±2.5 V
    • measured transient gain ≈ 7.025 V/V
  • This was not a verbatim TI OPA855 macro-model simulation.
  • The supplied TI .sub file is valid, but the built-in simulator cannot access uploaded include files.
  • The photon event was represented as an electrical hotspot surrogate, not an optical-field simulation.
Required release sequence
  1. Verify the OPA855 device-datasheet bypass network and restore the required local components.
  2. Obtain and apply PCB Power’s production stackup.
  3. Recalculate/tune VIN and VOUT for 50 Ω.
  4. Confirm SNSPD and wire-bond process data.
  5. Verify OptiCool mounting and connector geometry.
  6. Run fresh ERC, DRC, airwire, return-path, keepout, and Gerber inspections.
  7. Generate new Gerbers, drill files, IPC-D-356, BOM, and pick-and-place files.
  8. Submit to PCB Power for CAM/DFM review.
  9. Order a small bare-board/prototype quantity first.
Do not use earlier manufacturing exports: they predate major changes including the two-pad SNSPD footprint, routing updates, capacitor removal, L1 addition, and R3 output load.
A

anirudhiisc

hi

flux

Hi. The PCB is currently at the engineering-prototype stage, with supply decoupling, PCB Power stackup, SNSPD bonding requirements, and OptiCool mechanics still to be finalized before manufacturing release.
Check datasheet decoupling
Export release files
Review OptiCool fit
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Files

Schematic

Layout

Preview

DIE1
J4
J3
J2
J1
R3
Resistance
200Ω
L1
End of Life
Inductance
4.7µH
R1
Resistance
453Ω
OPA855: ±4.9 V is experimental cryogenic operation only; total supply exceeds the 5.5 V datasheet absolute maximum. NEVER apply ±4.9 V at room temperature. SNSPD bias: use J1 SNSPD_BIAS through R5=100 kΩ; target about 1.4–1.5 V for approximately 14–15 µA (Isw=16 µA), not 2 V/100 kΩ.
R4
Resistance
50Ω
R2
Resistance
75Ω
R5
Resistance
100kΩ
U1
TP3
TP1
TP2
C1