WARNING — PLACEHOLDER, NOT FABRICATION-QUALIFIED: The die-pad coordinates and real terminal map are unknown, and this geometry is based on explicit assumptions only. P1 and P2 now carry the provisional readout-model mapping described below; the other pads remain intentionally unconnected. Do not release for fabrication or bonding until every assumed value is replaced by detector-maker and bonding-lab approved data.

• Die outline: x = -16.0…-10.0 mm, y = -10.8…-4.8 mm.
• Working envelope: x = -18.0…-8.0 mm, y = -12.8…-2.8 mm.
• Left pad centers: x = -16.8 mm; y = -9.8, -8.8, -7.8, -6.8, -5.8 mm.
• Right pad centers: x = -9.2 mm; y = -9.8, -8.8, -7.8, -6.8, -5.8 mm.
• Every pad is 0.8 × 0.4 mm, rectangular, Top Copper SMD, connectedLayers = Top, mask expansion +0.05 mm, paste expansion -0.25 mm.
• Horizontal die-edge-to-pad copper gap is (0.8 mm row offset) − (0.4 mm pad half-width) = 0.4 mm on each side.
• Adjacent pad-center pitch is 1.0 mm in Y.
• The envelope bottom is 0.2 mm above the top of MH2 mounting-hole copper at y = -13.0 mm.

Text
                TOP

 PIN 1→P1  [ ]         [ ]  P10
        P2  [ ]         [ ]  P9
LEFT    P3  [ ]  DIE    [ ]  P8    RIGHT
        P4  [ ]  6×6    [ ]  P7
        P5  [ ]         [ ]  P6

              BOTTOM

1. Inspect before editing
   • Use PCB layout 2D/scene-tree inspection with components, pads, vias, routes, overlays and board outline visible.
   • Record full-project DRC results before editing so unrelated pre-existing findings remain distinguishable.
2. Change die size
   • Select layout node ASSUMED SNSPD Bare Die Outline 6x6mm.
   • Change rectangle start/end offsets symmetrically around its center, or set a new rectangle size.
   • Keep the node on Top Overlay; never change it to copper unless the backside requirement is known and explicitly approved.
3. Change terminal count
   • Add or delete footprint pad nodes under DIE1 using PCB layout-node operations.
   • Rename every pad explicitly (SNSPD Pn Bond Pad).
   • Recalculate numbering, endpoint labels and the pin-1 marker. Treat the present P1/P2 connectivity as provisional and replace it only from an approved terminal map.
4. Change pad dimensions
   • For each intended pad UID, set sizeX and sizeY, or recreate with geometry.size.
   • Keep padShape = rectangle, padHoleType = SMD, layer = Top Copper, and connectedLayers = Top unless approved data requires otherwise.
5. Change pitch
   • Keep each row at a constant X position.
   • Set successive Y centers from the selected datum using the approved pitch. Verify center-to-center differences from read-back coordinates rather than relying on the requested values.
6. Change pad-row positions and die-edge gap
   • Set left and right row X centers from the die edges and pad half-widths: row X = die edge ± (required copper gap + pad sizeX/2).
   • Set Y positions from actual die-pad coordinates and bond-tool approach, not from the outline alone.
7. Change mask opening
   • Set each pad’s solderMaskExpansion to the approved positive, zero or negative value.
   • Inspect Top Solder Mask and confirm the resulting opening dimensions in manufacturing output.
8. Suppress paste
   • Set solderPasteMaskExpansion sufficiently negative that both resulting aperture dimensions are non-positive. For the current 0.8 × 0.4 mm pads, -0.25 mm contracts each edge and fully suppresses the limiting 0.4 mm dimension.
   • Verify Top Solder Paste in Gerber/ODB++; do not rely only on editor appearance.
9. Change envelope or implement keepout
   • Resize/reposition SNSPD 10x10mm Working Envelope on Top Overlay for documentation.
   • Implement a real keepout only if it can exclude unrelated pads, vias, copper and components while explicitly allowing the ten intended lands. Re-run keepout/protected-intrusion DRC. If that cannot be represented robustly, keep the overlay envelope and state clearly that it is not enforced.
10. Re-label and verify
    • Keep all silk text at least 0.8 mm high and clear of copper, pads, holes and board edges.
    • Read back pad UIDs, positions, sizes, layers, mask/paste expansions, connected layers and any net/trace associations.
    • Run full-project DRC for overlaps, floating copper, invalid layers, dangling traces, board bounds, pad access, edge placement, keepouts and protected intrusions.

• Die nominal size, outline tolerance, thickness, edge condition, orientation mark and mechanical datum.
• Complete die bond-pad coordinates, dimensions, pitch, passivation openings and metallization stack.
• Terminal names, functions, polarity, detector bias/return arrangement and ESD handling requirements.
• Backside/substrate electrical requirement, backside metallization and whether conductive die attach or a backside bond is required.
• Approved die-attach material, bond-line thickness, cure cycle, placement tolerance and cryogenic/vacuum compatibility.
• Optical-access requirements: active-area location, field of view, fiber/beam clearance, allowable obstruction and contamination limits.
• Thermal-cycling limits, operating temperature, magnetic/thermal restrictions and acceptance tests.

• Wire material, diameter and bond method: wedge, ball, ribbon or other.
• Approved PCB bond-pad dimensions, shape, pitch, orientation, metallization and surface finish.
• Approved PCB finish and finish-thickness/roughness limits.
• Maximum wire length, loop height, loop profile, crossing restrictions and allowable approach angle.
• Tool/capillary/wedge clearance, fixture/clamp clearance and optical inspection access.
• Die-attach adhesive/process, cure profile, cleanliness, plasma cleaning and outgassing requirements.
• Maximum bond force, ultrasonic energy, temperature and die handling limits.
• Cryogenic and vacuum compatibility of wire, finish, adhesive, cleaning process and any encapsulant.
• Pull-test, shear-test, visual-inspection, rework and process-qualification criteria.

• Replace every assumption with controlled drawing data.
• Confirm real die-pad map, terminal names and polarity.
• Confirm backside electrical and die-attach requirements.
• Confirm approved wire, pad metallurgy, PCB finish and bonding method.
• Confirm actual wire length/loop height and tool clearance.
• Confirm optical access and cryogenic/vacuum compatibility.
• Create approved schematic connectivity and re-evaluate the high-frequency detector path.
• Verify zero paste and mask openings in Gerber/ODB++.
• Run and resolve manufacturing DRC with the actual geometry.
• Obtain written detector-maker and bonding-lab approval.

STOP: THE CURRENT P1/P2 ELECTRICAL ASSIGNMENT AND ALL TEN-PAD MECHANICAL ASSUMPTIONS ARE NOT FABRICATION-QUALIFIED.