SNSPD PCB Slot


PCB Release Notes — Current Revision
Project: Cryogenic DC-Coupled SNSPD Readout
Status: Engineering prototype; not approved for production or cryostat installation
Current design
  • PCB: 48 × 30 mm, four layers
  • Primary ground reference: solid L2 GND plane
  • SNSPD: centered 6 × 6 mm, two-terminal placeholder
    • Top-left pad: SIGNAL → VIN
    • Bottom-right pad: RETURN → GND
    • 7 × 7 mm die-attach area
    • Top illumination required
  • Bias path: J1 → R5 (100 kΩ) → L1 (4.7 µH) → VIN
  • Input network: AC-coupling capacitor into the OPA855 input and R4 = 50 Ω termination
  • Amplifier: OPA855
  • Feedback: R1 = 453 Ω, R2 = 75 Ω
    • Nominal closed-loop gain: 7.04 V/V
    • Equivalent gain: 16.95 dB
  • Output: VOUT → J2, with R3 = 200 Ω to GND
  • Supply inputs: J3 = positive rail, J4 = negative rail
  • Current intended operating rails: +2.5 V and −2.5 V
  • RF traces: VIN and VOUT, nominally 0.180 mm on L1, referenced to L2 GND
  • Latest reported routing status: zero airwires, dangling traces, and active ERC/DRC errors
Important hold points
  1. OPA855 decoupling is unresolved.
    The previous supply capacitors were removed. Exact local bypass requirements must be verified directly from the OPA855 device datasheet before release. A multi-GHz amplifier should not be fabricated without an approved supply-decoupling implementation.
  2. Stackup is provisional.
    The current “PCBWay Custom” stackup is not an approved PCB Power India stackup. Obtain:
    • exact four-layer construction
    • finished copper thicknesses
    • L1–L2 dielectric thickness and Dk
    • recommended L1 width for 50 Ω
    • impedance tolerance and coupon/test availability
  3. SNSPD footprint remains provisional.
    Confirm:
    • real die dimensions and thickness
    • exact bond-pad coordinates and metallurgy
    • signal and return pad locations
    • backside electrical requirements
    • approved die-attach material
  4. Wire-bond finish is unresolved.
    The PCB pads are exposed top-copper lands with solder paste suppressed. Select ENIG, ENEPIG, or soft gold only after agreement between the SNSPD supplier, bonding laboratory, and PCB Power.
  5. OptiCool mechanics remain provisional.
    • Board fits the nominal pod envelope in 2D.
    • Mounting-hole coordinates are not verified.
    • RF/DC feedthrough mating geometry and cable clearance are not confirmed.
    • Do not add or drill mounting holes from assumed dimensions.
  6. Cryogenic qualification is not established.
    • OPA855 operation on this exact PCB at 4 K is unverified.
    • L1 inductance, Q, self-resonance, and DC resistance at 4 K are unverified.
    • Connector, laminate, solder, adhesive, and capacitor behavior at 4 K require validation.
    • Results from the referenced paper do not automatically qualify this exact BOM or thermal arrangement.
Simulation status
  • Behavioral U1 transient:
    • J1 = 1.5 V
    • nominal bias = 15 µA
    • switching threshold = 20 µA
    • J3/J4 = ±2.5 V
    • measured transient gain ≈ 7.025 V/V
  • This was not a verbatim TI OPA855 macro-model simulation.
  • The supplied TI .sub file is valid, but the built-in simulator cannot access uploaded include files.
  • The photon event was represented as an electrical hotspot surrogate, not an optical-field simulation.
Required release sequence
  1. Verify the OPA855 device-datasheet bypass network and restore the required local components.
  2. Obtain and apply PCB Power’s production stackup.
  3. Recalculate/tune VIN and VOUT for 50 Ω.
  4. Confirm SNSPD and wire-bond process data.
  5. Verify OptiCool mounting and connector geometry.
  6. Run fresh ERC, DRC, airwire, return-path, keepout, and Gerber inspections.
  7. Generate new Gerbers, drill files, IPC-D-356, BOM, and pick-and-place files.
  8. Submit to PCB Power for CAM/DFM review.
  9. Order a small bare-board/prototype quantity first.
Do not use earlier manufacturing exports: they predate major changes including the two-pad SNSPD footprint, routing updates, capacitor removal, L1 addition, and R3 output load.
hi
Hi. The PCB is currently at the engineering-prototype stage, with supply decoupling, PCB Power stackup, SNSPD bonding requirements, and OptiCool mechanics still to be finalized before manufacturing release.
Check datasheet decoupling
Export release files
Review OptiCool fit

Readout Correction Report
Scope status
  • Completed — OPA855 gain network preserved: R1 remains 453 Ω from VOUT/FB to IN− and R2 remains 75 Ω from IN− to GND, for approximately 7.04 V/V (16.95 dB).
  • Completed — local supply decoupling: both OPA855 supply rails now have high-frequency and local bulk bypassing.
  • Completed — resistive SNSPD bias input: J1 is now the detector-bias connector and feeds VIN through R5 = 100 kΩ.
  • Completed — output load correction: the onboard R3 = 200 Ω VOUT shunt was removed; J2 remains the 50 Ω instrument/coax output.
  • Completed — PCB cleanup/routing: obsolete VIN/VOUT branches were removed and the revised nets were rerouted with no remaining airwires or dangling traces.
  • Completed — DIE1 mechanics preserved: the 6.0 × 6.0 mm body, centered 7.0 × 7.0 mm mounting area, bond-pad banks, and position were not altered.
Exact component changes
Added

Table


RefValue / partPackageFunction
C1100 nF, 25 V, C0G/NP0; KEMET C1206C104K3GECTU1206U1 VS+ high-frequency bypass to GND
C2100 nF, 25 V, C0G/NP0; KEMET C1206C104K3GECTU1206U1 VS− high-frequency bypass to GND
C32.2 µF, 16 V, X7R; TDK CGA4J3X7R1C225K125AB0805U1 positive-rail local bulk bypass to GND
C42.2 µF, 16 V, X7R; TDK CGA4J3X7R1C225K125AB0805U1 negative-rail local bulk bypass to GND
R5100 kΩ, 0.1%, 0.1 W; Panasonic ERA-3AEB104V0603Resistive feed from SNSPD_BIAS to VIN
Removed
  • R3 = 200 Ω, formerly from VOUT to GND.
  • Its PCB branch and the former J1-to-VIN copper branch were removed with the obsolete routing.
Final topology

Text


J1 center (SNSPD_BIAS) ── R5 100 kΩ ── VIN/readout node
                                            ├── DIE1 P1 (SPICE drain)
                                            ├── U1 IN+
                                            └── R4 50 Ω ── GND

DIE1 P2 (SPICE source) ── GND

U1 OUT/FB ── VOUT ── J2 center
       └── R1 453 Ω ── IN− ── R2 75 Ω ── GND
J1 shields, J2 shields, and all supply-connector shields remain on GND. SNSPD_BIAS is classified as an analog net. VIN and VOUT retain their 50 Ω controlled-impedance metadata and 0.17 mm PCB routing rule.
Final DIE1 electrical mapping

Table


Physical padElectrical roleFinal status
P1SPICE drainVIN/readout node
P2SPICE sourceGND return
P3SPICE gateIntentional NC; simulation-only photon control
P4SPICE gatereturnIntentional NC; simulation-only photon-control return
P5UnusedIntentional NC
P6Legacy visible SNSPD_RETURN padIntentional NC / isolated
P7–P10UnusedIntentional NC
This matches the uploaded subcircuit terminal order gate gatereturn drain source without adding a production photon-pulse source.
OPA855 support decisions
The OPA855 datasheet lookup was consulted before wiring. The returned extraction indicated:
  • PD low disables the amplifier and high enables normal operation, so the existing PD-to-V+S_RAW connection was preserved.
  • The exposed pad is to be tied to VS−, so the existing EP-to-V-S_RAW connection was preserved.
  • The supply pins require close high-frequency bypass capacitors and also recommend larger 2.2–6.8 µF local capacitors farther from the device.
Verification status: the datasheet tool returned these facts through an uncited OCR fallback, so they are recorded as consulted but not provenance-cited here. The implementation uses 100 nF C0G/NP0 close-in bypasses and 2.2 µF X7R bulk capacitors.
Cryogenic capacitor assumption
C0G/NP0 was selected for the 100 nF parts to favor temperature and voltage stability. A commercially available 100 nF C0G part requires the larger 1206 package. The 2.2 µF bulk parts use X7R because practical C0G parts are not available at this capacitance. The effective X7R capacitance and ESR at 4 K must be characterized on the assembled hardware; this is an intentional remaining engineering warning.
Output-load decision
The 200 Ω onboard VOUT shunt was removed. With the external 50 Ω instrument connected, leaving R3 would have produced an effective load of 40 Ω. The final board relies on the external 50 Ω coax/instrument termination only.
Safety and operating notes
  • ±4.9 V is experimental cryogenic operation only. It exceeds the OPA855 5.5 V total-supply absolute maximum and must never be applied at room temperature.
  • Use J1 with an adjustable source around 1.4–1.5 V through R5 = 100 kΩ to target approximately 14–15 µA for a detector with Isw = 16 µA.
  • Do not use the reference simulation's 2 V / 100 kΩ setting as the normal operating point; it approaches 20 µA and exceeds the stated switching-current target.
PCB implementation and verification
  • C1 and C2 were placed near U1's VS+ and VS− pads with short, wide rail connections and nearby ground returns.
  • C3 and C4 were placed farther from U1 and connected with 0.5 mm rail traces.
  • R5 was placed immediately left of the DIE1 working envelope, close to P1, while preserving the detector geometry.
  • VIN and VOUT were rerouted without the former connector/load stubs.
  • Deterministic U1 neckdowns were generated before rerouting.
Final live checks:
  • Airwires: 0
  • Dangling traces: 0
  • Overlapping copper/traces: no open findings
  • Critical ERC/DRC findings: none
  • Intentionally remaining manufacturing warning: DIE1 has no manufacturer part number because it is a custom assumed placeholder.
  • Intentionally remaining physical warning: the DIE1 bond-pad geometry is still provisional and not fabrication-qualified without detector-maker and bonding-lab data.