Design for Manufacturing Checklist
Help me prepare this design for manufacturing. Walk me through a comprehensive checklist:
- Generate and review the Bill of Materials — check for missing MPNs, availability issues, and cost optimization
- Run design rule checks — verify all electrical connections, check for unconnected pins and floating nets
- Review passive component consolidation opportunities to simplify the BOM
- Verify all component footprints and packages are correct for assembly
- Create a test plan for board bring-up
Start with the BOM review and work through each step.
Thought for 7 sec
I can’t start the manufacturing-prep workflow because this account currently has no available ACUs, so AI tool execution is unavailable right now.
Nothing has been changed in the project during this session. Remaining work once ACUs are available:
- Generate and review the BOM for missing MPNs, lifecycle/availability risks, and cost optimization.
- Run ERC/DRC checks for unconnected pins, floating nets, airwires, clearance issues, and manufacturing-rule violations.
- Consolidate passive values/packages where practical to reduce BOM line items.
- Verify every footprint/package against the intended assembly process and component datasheets.
- Create a board bring-up test plan covering power rails, programming, ESP32 boot, sensors/load-cell path, USB/power behavior, and functional validation.
When ACUs are available, I’d start with the BOM review exactly as requested, then proceed through the checklist in order.
Manual BOM checks
Test plan template
Footprint checks
Passive consolidation
Export BOM help
![ESPRSSO32 Smart Scale AI Auto Layout [Example] thumbnail](https://img-cdn.flux.ai/eyJidWNrZXQiOiJncmF2aXRvbi1lbGVjdHJpYy1zeW1ib2xzIiwia2V5IjoiZG9jdW1lbnRfYXNzZXRzL0VTUFJFU1NPMzJfU21hcnRfU2NhbGVfM0RfVGh1bW5haWwtY2QxNTI2NjItNjdjMi00MTk4LWJmNjUtNDJiZDk5N2E0ODYyLnBuZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6MTM2LCJoZWlnaHQiOjEzNiwiZml0IjoiY29udGFpbiIsImJhY2tncm91bmQiOnsiciI6MCwiZyI6MCwiYiI6MCwiYWxwaGEiOjB9fX0sIm91dHB1dEZvcm1hdCI6IndlYnAifQ==)