PCB Design for PV Module Controller

flux

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Work done
  • Created and populated the Project Specification file with the Board A hierarchical architecture, Mermaid block diagram, power/signal flow, grounding/layout notes, and initial sourcing notes.
  • Renamed the project to Board A LV Controller.
  • Added the first-pass schematic components for the power-input and MCU subsystem: 24V Phoenix input connector, 3A input fuse/PTC placeholder, P-MOSFET reverse protection, SMBJ30A TVS, TPS54331 buck regulator, AP2112K-3.3 LDO, STM32H743VIT6 MCU, 25MHz HSE crystal, USB-C connector, reset/BOOT0 buttons, status LEDs, and support resistors.
  • Verified key datasheet details for STM32H743VIT6 power/clock/debug/USB pins, TPS54331 support requirements, and AP2112K-3.3 capacitor/EN requirements.
  • Confirmed Flux library distributor metadata for several major parts showing Mouser/Digi-Key availability: STM32H743VIT6, TPS54331DR, AP2112K-3.3TRG1, DMG2305UX-7, USB4105-GF-A, PTS645 switch, and Phoenix 1757242.
Success criteria review
  • ✅ Hierarchical block diagram: saved in Project Specification.
  • ⚠️ Power-input and MCU schematic: core parts were added, but wiring and remaining support passives were not completed.
  • ⚠️ India stock documentation: library distributor metadata was recorded for selected parts, but live regional stock verification remains to be completed.
  • ❌ Initial review/connectivity integrity: not yet complete because schematic wiring and support components still need to be finished.
Next steps
When execution can continue, the remaining work is to wire the power chain and MCU pins, add TPS54331 inductor/diode/feedback/compensation caps, add STM32 decoupling/VCAP/VDDA passives, add SWD header and USB-C CC/ESD parts, then run the schematic review. After the schematic is complete, the natural next stage is PCB layout setup: board sizing, 4-layer stackup, placement, and routing.
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Board A LV Controller — Project Specification
Scope
Board A is the per-channel low-voltage controller PCB for a PV module test power supply supporting TC/HF/LeTID workflows per IEC 61215 and IEC TS 63342. This PCB commands a separate isolated power stage and senses the DUT; the high-power isolated stage is not implemented on this board.
Initial Implementation Focus
  1. Hierarchical block diagram and signal/power flow.
  2. Power-input, protection, regulation, and STM32H743 MCU core schematic.
  3. Sourcing notes for parts available from Mouser/Digi-Key India where library availability metadata is present.
Hierarchical Architecture
Diagram



  
    
  
  
    
  
















































24V Cabinet Bus Input
Input Protection: Fuse, PMOS Reverse Protection, SMBJ30A TVS
5V Digital Buck: TPS54331 or LM2596
3V3 Digital LDO: AP2112K-3.3
Isolated DC-DC: RH-0515D Class Module
Analog Rails: Isolated +15V and -15V
Isolated node_5V Digital and node_5V Analog Domains
STM32H743VIT6 MCU Core
SWD Debug Header
USB-C Firmware Update Interface
25MHz HSE Crystal
Reset and BOOT0 Buttons
Status LEDs
Future DAC Block: DAC8563 and OPA2188
Future Isolated Analog Output: AMC1200 or ISO224
Future ADC Block: ADS1263, Divider, INA240A3
DUT 4-Wire Kelvin Sense Terminal
Future PT100 Block: MAX31865
Future Humidity Probe: SHT35 I2C JST
Future Gate Driver Digital Isolation: Si8662BD or ISO7741
Future Ethernet: LAN8720A and MagJack
Future CAN: TCAN1051
Future Interlocks and Outputs
Future EEPROM and RTC
Grounding and Layout Requirements
  • Board target: 100 mm x 80 mm, 4-layer, 1.6 mm FR4, ENIG.
  • Use distinct AGND and DGND regions with one star connection under the ADC area in the later analog/ADC implementation.
  • Keep switching regulator power loops compact and away from ADC/DAC/reference circuitry.
  • Place HSE crystal within 5 mm of STM32 oscillator pins with grounded guard/pour where practical.
  • Decouple each STM32 power pin locally; VCAP pins require local 2.2uF capacitors and must not be tied to an external rail.
Initial Component Selection Notes
  • MCU: STMicroelectronics STM32H743VIT6, LQFP100. Flux library metadata indicates Digi-Key and Mouser availability.
  • 5V buck: Texas Instruments TPS54331DR, 3A adjustable buck regulator. Flux library metadata indicates Digi-Key and Mouser availability.
  • 3.3V LDO: Diodes Incorporated AP2112K-3.3TRG1, 600mA SOT-23-5. Flux library metadata indicates Digi-Key and Mouser availability.
  • Input TVS: SMBJ30A family, SMB package. Candidate library part: Diodes Incorporated SMBJ30A-13-F.
  • Isolated +/-15V converter: RECOM RH-0515D or footprint-compatible equivalent to be confirmed during the rail-isolation sub-block pass.
Follow-Up Blocks
DAC/setpoint, isolated analog output, ADS1263 4-wire sense ADC, PT100, humidity probe, isolated gate-driver interface, Ethernet, CAN, interlocks, EEPROM, and RTC will be added in later schematic iterations.

    Scope

    Initial Implementation Focus

    Hierarchical Architecture

    Grounding and Layout Requirements

    Initial Component Selection Notes

    Follow-Up Blocks

Documents

    Board A LV Controller — Project Specification

Assets

Assets are files uploaded to this project which can be used in various ways.

Board A LV Controller thumbnail
Per-channel low-voltage controller PCB for RIL TC/HF/LeTID and PID test benches. STM32H7, 16-bit DAC setpoints, 24-bit ADC sense (4-wire), isolated digital interface to gate driver, PT100/RH conditioning, Ethernet, interlocks. Safety-critical brain board.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$10.16–$10.91

Digi-Key

$18.45–$19.40

HQonline

$1.27

LCSC

$9.40–$11.68

Mouser

$18.35

TME

$15.17

Verical

$8.92–$21.84

Controls