PCB Design for PV Module Controller

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I was unable to continue the implementation because execution credits are currently exhausted. Before stopping, I retrieved the current schematic state, confirmed the power-input subsystem initially had no nets, found/selected library parts for the required power components, replaced the placeholder reverse-protection MOSFET with Q_PWR / DMP3056L-7, and added the required non-generic power parts: D_ZG 10V Zener, D_SW SS34 catch diode, L1 10uH buck inductor, FB_5VA and FB_3V3A ferrite beads, and D_PWR LTST-C190KGKT power LED. Several required passives already appear to exist or were partially added, including the feedback/compensation/gate/LDO resistors and buck/input capacitors, but the subsystem is not yet wired and no schematic review could be run. Remaining work: verify all passive values, add any missing LDO/analog-filter capacitors, wire the +24V input chain, TPS54331, AP2112K-3.3, analog rail filters, and power-good LED, then run a scoped POWER INPUT schematic review for floating pins and missing power nets only.

flux

I’m unable to continue executing the remaining schematic changes because the session can no longer perform project-modification actions. So far, I replaced the placeholder MOSFET with Q1 DMP3056L-7, renamed the Phoenix input connector to J_PWR, and added the required POWER INPUT support parts for the +24V chain, TPS54331 buck, AP2112K LDO, analog rail ferrite filters, and +3V3 power-good LED. Wiring, no-connect marking for unused pins, and the final targeted schematic review still remain to be completed.

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Board A LV Controller — Project Specification
Scope
Board A is the per-channel low-voltage controller PCB for a PV module test power supply supporting TC/HF/LeTID workflows per IEC 61215 and IEC TS 63342. This PCB commands a separate isolated power stage and senses the DUT; the high-power isolated stage is not implemented on this board.
Initial Implementation Focus
  1. Hierarchical block diagram and signal/power flow.
  2. Power-input, protection, regulation, and STM32H743 MCU core schematic.
  3. Sourcing notes for parts available from Mouser/Digi-Key India where library availability metadata is present.
Hierarchical Architecture
Diagram



  
    
  
  
    
  
















































24V Cabinet Bus Input
Input Protection: Fuse, PMOS Reverse Protection, SMBJ30A TVS
5V Digital Buck: TPS54331 or LM2596
3V3 Digital LDO: AP2112K-3.3
Isolated DC-DC: RH-0515D Class Module
Analog Rails: Isolated +15V and -15V
Isolated node_5V Digital and node_5V Analog Domains
STM32H743VIT6 MCU Core
SWD Debug Header
USB-C Firmware Update Interface
25MHz HSE Crystal
Reset and BOOT0 Buttons
Status LEDs
Future DAC Block: DAC8563 and OPA2188
Future Isolated Analog Output: AMC1200 or ISO224
Future ADC Block: ADS1263, Divider, INA240A3
DUT 4-Wire Kelvin Sense Terminal
Future PT100 Block: MAX31865
Future Humidity Probe: SHT35 I2C JST
Future Gate Driver Digital Isolation: Si8662BD or ISO7741
Future Ethernet: LAN8720A and MagJack
Future CAN: TCAN1051
Future Interlocks and Outputs
Future EEPROM and RTC
Grounding and Layout Requirements
  • Board target: 100 mm x 80 mm, 4-layer, 1.6 mm FR4, ENIG.
  • Use distinct AGND and DGND regions with one star connection under the ADC area in the later analog/ADC implementation.
  • Keep switching regulator power loops compact and away from ADC/DAC/reference circuitry.
  • Place HSE crystal within 5 mm of STM32 oscillator pins with grounded guard/pour where practical.
  • Decouple each STM32 power pin locally; VCAP pins require local 2.2uF capacitors and must not be tied to an external rail.
Initial Component Selection Notes
  • MCU: STMicroelectronics STM32H743VIT6, LQFP100. Flux library metadata indicates Digi-Key and Mouser availability.
  • 5V buck: Texas Instruments TPS54331DR, 3A adjustable buck regulator. Flux library metadata indicates Digi-Key and Mouser availability.
  • 3.3V LDO: Diodes Incorporated AP2112K-3.3TRG1, 600mA SOT-23-5. Flux library metadata indicates Digi-Key and Mouser availability.
  • Input TVS: SMBJ30A family, SMB package. Candidate library part: Diodes Incorporated SMBJ30A-13-F.
  • Isolated +/-15V converter: RECOM RH-0515D or footprint-compatible equivalent to be confirmed during the rail-isolation sub-block pass.
Follow-Up Blocks
DAC/setpoint, isolated analog output, ADS1263 4-wire sense ADC, PT100, humidity probe, isolated gate-driver interface, Ethernet, CAN, interlocks, EEPROM, and RTC will be added in later schematic iterations.

  • Scope

  • Initial Implementation Focus

  • Hierarchical Architecture

  • Grounding and Layout Requirements

  • Initial Component Selection Notes

  • Follow-Up Blocks

Documents

Assets

Assets are files uploaded to this project which can be used in various ways.

Board A LV Controller 00e9 thumbnail
Per-channel low-voltage controller PCB for RIL TC/HF/LeTID and PID test benches. STM32H7, 16-bit DAC setpoints, 24-bit ADC sense (4-wire), isolated digital interface to gate driver, PT100/RH conditioning, Ethernet, interlocks. Safety-critical brain board.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$10.90–$12.50

Digi-Key

$18.58–$20.96

HQonline

$8.60–$8.66

LCSC

$10.75–$13.80

Mouser

$26.06–$26.22

TME

$15.30

Verical

$10.02–$24.56

Controls