Minimal CM5 Project Design

A

amirkat

Add the minimum required set of components needed to run a simple project using the CM5. Keep the design as minimal and practical as possible while ensuring the module can boot and operate reliably.
Include only the essential supporting circuitry: Power input and regulation Decoupling capacitors Required clocks or pull-ups/pull-downs
Avoid unnecessary features or complex expansion circuitry Optimize for simplicity and fast prototyping Keep the BOM as small as possible

flux

I’ll build the smallest practical CM5 support schematic: first I’ll inspect the CM5 pinout and requirements, then add only the essential power/regulation, decoupling, and required biasing, wire it, and run checks.

flux

Minimum architecture selected: regulated 5 V enters through USB-C, CM5 handles its onboard 3.3 V/1.8 V regulation, and GPIO_VREF will be tied to CM5_3.3V for normal 3.3 V GPIO. I’m adding only the USB-C input, VBUS protection, and two input capacitors.

flux

Wiring is complete. The remaining ERC items are expected unused CM5 interfaces and unused USB-C data/SBU pins, so I’m marking them explicitly as no-connect rather than adding expansion circuitry.

flux

Done — I added a minimal CM5 bring-up schematic: USB-C 5 V input, VBUS TVS protection, 100 µF + 100 nF input capacitance, CC1/CC2 to the CM5, all 5 V/GND pins wired, GPIO_VREF tied to CM5_3.3V, and unused interfaces explicitly marked no-connect.
I also created Minimal CM5 Bring-Up Notes with the BOM, power budget, datasheet assumptions, and validation notes. Remaining review items are layout-stage airwires because the board is not placed/routed yet; U1:VBUS_EN is intentionally unused for this minimal boot-only design.
Proceed to layout
Add power switch
Add boot access
Use barrel input
Review BOM
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Files

Schematic

Layout

Preview

J1
U1
Manufacturer Part Number
Raspberry Pi Compute 5
D1
J1 CC1 - U1 CC1
C2
Capacitance
0.1 uF
J1 VBUS__1 - U1 +5V(INPUT)
GND
J1 SHIELD - J1 SHIELD__1
J1 SHIELD - J1 SHIELD__1
U1 CM4_3.3V(OUTPUT)__1 - U1 GPIO_VREF
J1 CC2 - U1 CC2
J1 SHIELD - J1 SHIELD__1
C1
Capacitance
100 uF
U1 CM4_3.3V(OUTPUT)__1 - U1 GPIO_VREF
J1 CC2 - U1 CC2
U1 +5V(INPUT)__5 - D1 1
J1 SHIELD - J1 SHIELD__1
GND
U1 +5V(INPUT)__5 - D1 1
J1 SHIELD - J1 SHIELD__1
U1 +5V(INPUT)__5 - D1 1
J1 SHIELD - J1 SHIELD__1
J1 CC1 - U1 CC1
J1 VBUS__1 - U1 +5V(INPUT)
J1 SHIELD - J1 SHIELD__1
U1 CM4_3.3V(OUTPUT)__1 - U1 GPIO_VREF
GND
J1 SHIELD - J1 SHIELD__1
U1 +5V(INPUT)__5 - D1 1
Minimal CM5 Bring-Up Notes
Scope
This schematic keeps only the minimum practical circuitry required to power and boot a Raspberry Pi Compute Module 5 carrier board prototype.
Datasheet-grounded requirements used
  • CM5 requires a regulated 5 V input rail from 4.75 V to 5.25 V.
  • CM5 power supply should accommodate 5 V at up to 2.5 A for peak load.
  • PMIC_ENABLE is internally pulled up to 5 V through 100 kΩ and may be left undriven for normal boot.
  • nRPIBOOT is internally pulled up through 10 kΩ to CM5_3.3V and may be left floating for normal eMMC boot.
  • EEPROM_nWP is internally pulled up through 100 kΩ to CM5_3.3V and may be left floating when write protection is not required.
  • GPIO_VREF must not float; it is tied to CM5_3.3V for standard 3.3 V GPIO signalling.
  • CM5 exposes CC1 and CC2 specifically for USB-C power negotiation up to 5 V / 5 A; these are wired directly to the USB-C connector CC pins.
Added minimal BOM

Table

DesignatorFunctionValue / MPNNotes
J1USB-C power inputUJ20-C-H-G-SMT-2-P16-TRUses VBUS, GND, CC1, CC2 only. USB data/SBU pins intentionally no-connect.
D1VBUS protectionSMF5.0A5 V TVS from 5 V rail to GND.
C15 V bulk capacitor100 uF, Murata GRM32ER61A107ME20LEffective capacitance must be checked for MLCC DC-bias at 5 V.
C25 V HF bypass100 nF, Samsung CL10B104KB8NNNC / LCSC C15910603 X7R bypass on the 5 V rail.
Power budget
  • CM5 typical idle current: 400 mA.
  • CM5 typical operating current: 900 mA.
  • CM5 carrier supply target: 5 V at up to 2.5 A per datasheet guidance.
  • USB-C connector selected for a 5 A-capable path; final layout must use adequate copper for 2.5 A continuous/peak operation.
Intentional omissions for minimal BOM
  • No Ethernet, HDMI, PCIe, MIPI, SD, fan, GPIO headers, LEDs, buttons, or USB data routing.
  • PMIC_ENABLE, nRPIBOOT, EEPROM_nWP, PWR_Button, and unused interfaces are intentionally no-connect or left to internal pulls per datasheet behavior.
  • VBAT is tied to CM5_3.3V for a no-battery prototype RTC supply during powered operation; add a coin-cell circuit later if RTC retention is required while unpowered.
Validation notes
  • Schematic ERC floating-pin warnings were cleared by explicit no-connect markers for intentionally unused signals.
  • Remaining design review airwires are PCB routing-stage findings because the newly added nets have not been placed/routed yet.
  • U1:VBUS_EN is intentionally unused in this minimal design; it is a USB VBUS enable/control signal for designs that implement downstream USB power switching, not required for basic CM5 boot from eMMC.
Layout guidance for next phase
  • Place J1 on a board edge.
  • Place D1, C1, and C2 close to J1 / CM5 5 V entry.
  • Use wide 5 V and GND copper for 2.5 A capability.
  • Keep all GND pins stitched to a solid ground plane.

  • Scope

  • Datasheet-grounded requirements used

  • Added minimal BOM

  • Power budget

  • Intentional omissions for minimal BOM

  • Validation notes

  • Layout guidance for next phase