Wearable BCI Design Discussion

Work done
  • SWD programming: verified existing 2x3 SWD header PROG is wired to U3 on nets SWDIO, SWDCLK, 3V3_D, and GND.
  • BQ25895 support: added the required 47 nF BTST bootstrap cap C5 between U4 BTST and SW; verified the JST-PH 2-pin battery connector J4 is connected to BAT and GND; verified SYS from U4 feeds both LDO1 IN and LDO2 IN.
  • Dual-LDO isolation: ensured LDO1 serves the 3V3_D rail (MCU/USB) and LDO2 serves the 3V3_A rail (analog); connected 3V3_A to U2 AVDD1 and added C6 (SYS input decoupling) and C7 (3V3_A output decoupling).
Placement prep (manual guidance)
  • Quiet Zone (9:00): place J1 on the left edge; put D1/D2 between J1 and U2; place U2 immediately to the right of J1.
  • Noisy Zone (3:00): place J2 top-right; place U4 + L1 just below J2; place battery connector J4 adjacent to U4.
  • Bridge Zone (6:00): place U3 bottom-center/right; place PROG along the bottom edge.
  • Decoupling proximity rule: move each IC’s local decouplers (e.g., C5, C6, C7, C1, C2) to be as close as physically possible to the corresponding power pins.
Routing handoff (deferred)
  • Plan: bottom-layer GND pour; top-layer 0.5 mm power trunk; keep top-layer sensor inputs as short as possible; route SPI on bottom layer.
Success criteria review
  • ✅ SWD header added/connected to U3
  • ✅ BQ25895 improvements implemented: C5, J4, SYS->both LDOs
  • ✅ Dual-LDO isolation implemented with distinct 3V3_D and 3V3_A
  • ✅ Placement-zone guidance provided (Quiet/Noisy/Bridge) + decoupling proximity guidance
  • ✅ Routing guidance documented; routing intentionally deferred
Next steps
  • I cannot auto-place or auto-route. After you place parts, run Auto-Layout for routing and I will re-check airwires/DRC and iterate placement tweaks if needed.
U2
J3
U1
GND
R1
Resistance
10kΩ
GND
GND
GND
GND
GND
GND
U4 BAT - J4 P1
U4 BAT - J4 P1
LDO2 OUT - C7 P1
U3 SWDIO - PROG 1
LDO2 OUT - C7 P1
U4 BTST - C5 P1
U4 SYS - LDO1 IN
U3 SWDCLK - PROG 2
U4 SW - C5 P2
U3 SWDCLK - PROG 2
U3 SWDIO - PROG 1
U4 BTST - C5 P1
LDO2 OUT - C7 P1
U3 VDD - PROG 3
U4 SYS - LDO1 IN
U4 SW - C5 P2
U4 SYS - LDO1 IN
U4 SYS - LDO1 IN
U3 VDD - PROG 3
J1
PROG
D2
J4
C1
Capacitance
100 nF
C7
Capacitance
1uF
C5
Capacitance
47nF
D1
U3
Not Recommended for New Designs
C4
Capacitance
10pF
C3
Capacitance
10pF
C6
Capacitance
1uF
C2
Capacitance
100 nF
LDO1
U4
L1
Inductance
4.7 uH
LDO2
Y1
J2

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    8-Channel Wearable BLE5 Brain–Computer Interface with 24-bit Biopotential AFE and Cross-Platform SDKs

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    "Power Subsystem" "Biopotential AFE/ADC" "BLE MCU/SoC" "Electrode Connector" "Status LEDs"

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