Fixing Copper Shorting Error
0:00
Work done
- Renombré el proyecto a Portable Potentiostat.
- Verifiqué en el esquemático que J2 solo tiene dos terminales eléctricos válidos: POS -> VBAT_RAW y NEG -> GND.
- Inspeccioné el layout de J2 y confirmé la causa del problema: además de los pads reales POS y NEG, el footprint contiene pads extra P y N en las mismas coordenadas, creando cobre superpuesto.
- Intenté neutralizar esos pads duplicados aplicando reglas de layout sobre los pads extra del footprint.
- Reejecuté la revisión del layout para comprobar el resultado.
Success criteria review
- ❌ El error de Overlapping Copper en J2 no se eliminó completamente.
- ✅ Las conexiones eléctricas previstas del conector siguen claras en el esquemático: J2 mantiene VBAT_RAW y GND en sus terminales correctos.
- ❌ La revisión final del layout no quedó limpia: siguen apareciendo errores de Overlapping Copper y también Airwires.
Next steps
Queda pendiente una corrección que requiere editar o sustituir directamente el footprint/part de J2 para eliminar físicamente los pads extra P/N. En esta sesión no puedo continuar ejecutando cambios adicionales, pero el siguiente paso correcto es reemplazar ese footprint por una versión con solo POS y NEG, y luego volver a revisar DRC completo.
20 days
0:31
Reviewing the bill of materials.
Analyzing the schematic.
Analyzing component removal.
Sí, ya los quité:
Al eliminar componentes, también se destruyen sus conexiones asociadas; eso es el comportamiento esperado del flujo de modificación del proyecto
Si quieres, el siguiente paso puede ser uno de estos:
Revisa nets abiertas
Limpia errores layout
Quita resistencias LED
20 days
Removed 2 components
0:10
Removed J2
Removed D1
⚠️ Removed components had their net connections destroyed. Use the connections tool with a `view` action to verify connectivity and re-wire any lost connections.
20 days
Refine this doc
Ask about this doc
Design Notes
Potentiostat requirements
- Field-deployable heavy-metal measurement instrument
- Very low current measurement priority
- Standalone low-noise operation from clean power source
- Multiple voltammetric techniques supported by external control logic
- Derived from LMP91000 EVM concept, but stripped of noisy evaluation-only circuitry
Findings from uploaded references
- Use the LMP91000 as the potentiostat core.
- Preserve external RTIA option using the footprint/function of R3 to tailor current range.
- Preserve external analog filtering using the footprint/function of C2 and the anti-alias network around the ADC path.
- Operate in standalone mode by disconnecting noisy USB-derived power path.
- Prefer external precision VREF injected directly into VREF pin when higher stability is required.
- Remove EEPROM and unnecessary jumper/traffic that injects digital noise.
- Consider omitting JFET shorting protection in the highest-sensitivity variant to reduce leakage, while noting the robustness tradeoff.
- Use pseudo-differential ADC measurement relative to VREF to suppress zero-shift and dedicate dynamic range to electrochemical signal changes.
- Keep analog and digital grounds partitioned and join them at a single star point near power entry.
- Shield the sensor and front-end using a Faraday enclosure tied to AGND.
Initial architecture decision
- Build a custom board derived from the EVM concept rather than copying the EVM wholesale.
- Partition into: sensor connector, potentiostat AFE, ADC/filter/reference, MCU control, low-noise power, and calibration/test access.
- Use separate low-noise analog and digital 3.3 V rails.
- Include selectable RTIA/filter ranges for low-current optimization and technique flexibility.
Concrete continuation plan
- Use the exact LMP91000 device family as the potentiostat AFE when available in library.
- Keep the ADC161S626 path if available in library; otherwise substitute a practical 16-bit single-supply ADC with SPI and similar input range for the first prototype.
- Prefer a low-noise 3.3 V LDO family stable with ceramic capacitors for both analog and digital rails, with separate instances for analog and digital partitioning.
- Prefer an external 2.5 V precision reference for VREF and pseudo-differential ADC measurement.
- Use a hand-solderable 3-position electrode connector in the first prototype, favoring robust field wiring over miniature density.
- Capture the first schematic as a minimum viable low-noise core, then add MCU, user interface, and calibration hooks in a second pass.
Implemented first-pass schematic core
- U1 = LMP91000, used as the electrochemical AFE with WE, RE and CE routed to a 3-position field connector.
- U2 = ADS1120, used as the first available 16-bit ADC substitute for the unavailable ADC161S626 library part.
- IC1 = LT6657-2.5 precision reference feeding VREF and the negative side of the pseudo-differential ADC path.
- U3 and U4 = separate low-noise 3.3 V regulators for analog and digital rail partitioning.
- U5 = ATSAMD10C13A-SS hand-solderable controller for I2C configuration and SPI readout.
- R3 and C10 were reserved as the external RTIA and compensation placeholders derived from the EVM R3/C2 concept.
- R4/R5 with C7/C8 implement the initial pseudo-differential anti-alias/filter network around the ADC inputs.
- The current schematic is an architectural prototype and still needs the second pass for battery protection, programming/debug connector, user controls, and final analog optimization.
Unused-pin and DNC closure decisions
- LT6657-2.5 DNC pins 1, 5, 7, and 8 must remain floating. The datasheet states these pins are internally connected and external circuitry must not be attached.
- ADS1120 CLK is tied to ground to force the internal oscillator.
- ADS1120 AIN2 is tied to AVDD/3V3_A as a defined unused analog input.
- ADS1120 AIN3/REFN1 is intentionally left floating because the datasheet calls it out as the exception that should remain open when unused.
- ADS1120 ~DRDY is not used by firmware and is held high with a weak pull-up.
- ATSAMD10 unused pins PA02, PA08/XIN, and PA09/XOUT are biased with weak 100 kOhm pulldowns and should still be configured to a defined state in firmware.
- The SS12F44G5 slide switch is used as SPST battery on/off; the unused throw is intentionally left unconnected because the switch is 1P2T non-shorting with a center common terminal.
Schematic closure status
- Fixed the accidental I2C short that had tied SCL, SDA, and both pull-up resistors directly to 3V3_D.
- Created proper I2C_SCL and I2C_SDA nets between U5, U1, and pull-ups R1/R2.
- Verified that the shorted-component ERC warnings on R1 and R2 are cleared.
- Remaining ERC warnings are intentional only: LT6657 DNC pins, ADS1120 AIN3/REFN1 left open per datasheet, and the unused SPDT throw on the power switch.
- This schematic is now considered v1-complete and ready for schematic review or PCB layout preparation.
PCB bring-up and cleanup status
- Layout outline is set to 100 mm x 100 mm with 2 mm corner radius and 0.25 mm board inset margin.
- Stackup remains a 4-layer build with Layer 2 intended as a continuous GND reference plane and Layer 3 as the power distribution plane.
- Current layout density is low enough to support a clean analog/digital floorplan; placed components occupy about 71 mm x 69 mm inside the outline.
PCB zoning and grounding intent
- Analog zone should contain J1, U1, U2, IC1, J4, R7, R8, R9, C10, R4, R5, C7, and C8.
- Digital and power zone should contain J2, SW1, U3, U4, U5, J3, reset circuitry, indicator LED, and the digital pull-up/pulldown network.
- Keep VREF_2V5, AFE_OUT, ADC_IN_P, WE, RE, CE, RTIA_NODE_1, and RTIA_NODE_2 short and isolated from SWD and SPI clock routing.
- Implement AGND/DGND behavior by placement and return-current control only; do not split the schematic ground net. The single tie behavior should occur near power entry, while keeping Layer 2 unbroken beneath the reference, ADC, and AFE.
Current PCB rule intent
- Sensitive analog nets VREF_2V5, AFE_OUT, and ADC_IN_P use 0.20 mm routing with 0.50 mm keepout margin.
- VBAT_RAW should remain wide at 0.80 mm and 3V3_D at 0.50 mm.
- SWCLK_DBG and SWDIO_DBG may remain narrow at 0.18 mm and should be kept out of the analog zone.
- LDOA_FB and LDOD_FB should remain short and local to their regulators.
Current DRC triage notes
- Overlapping copper errors currently map to these placed parts: R1, J2, an additional unresolved pad with uid prefix ab05d331, and J4.
- The repeated J2 and J4 overlap checks indicate footprint-local copper conflicts or pad-to-mechanical copper conflicts, not broad board-density limitations.
- Because the layout editing toolset available in this run does not include direct component placement or copper geometry editing, those overlap issues still need footprint-level or placement-level cleanup in the PCB editor.
- Airwires remain high and indicate that the board is still in pre-routing floorplan stage rather than final routing stage.
Acceptable remaining warnings
- Floating IC1 DNC pins are intentional and must remain without copper.
- U2 AIN3/REFN1 remains intentionally open.
- SW1 unused throw remains intentionally unconnected.
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.