flux

## Updated brief — 16‑channel automotive audio DSP main board (100 mm × 100 mm, 4‑layer)

### High-level goal

Design a high‑performance automotive DSP main board for a 16‑channel car audio processor in Flux EDA, prioritizing excellent audio performance/low noise, modular balanced outputs to an external RCA board, compact manufacturable layout, and strict routing discipline (quiet clock corridor, TDM corridor, analog shielding, ESP32 RF isolation).

### What’s been completed

1. **Architecture definition refined (no redesign):** A layout‑ready system block diagram was produced showing:

- SPDIF → receiver → **I2S** → ADAU1467 → **TDM8** → 2× AK4458 → analog chain → balanced connector → external RCA board.

- Clock island: oscillator → NB3L553 → DSP/DACs.

- Power tree intent: 12 V → buck 5 V → multiple LDO rails with analog/digital isolation.

- Control: ESP32 → I2C → DSP (+ optional SPDIF control), UART debug.

- PCB functional zones and signal-flow placement order.

2. **Routing/SI constraints finalized and documented as project intent:**

- TDM bus corridor rules (grouped, similar length, minimal stubs/vias, symmetric fanout).

- Quiet clock corridor rules (short/direct over continuous GND, avoid buck/ESP32, minimize vias, avoid parallelism to buses).

- DAC differential analog pair constraints (tight coupling, equal length, stay in analog region).

- Analog region shielding rules (no digital crossings, continuous GND reference, guard traces/via fencing where appropriate).

- Connector routing consistency and ESP32 RF isolation rules.

3. **Board mechanical intent updated:**

- Board size updated to **100 mm × 100 mm** for this revision; 4‑layer intent retained (L2 continuous GND, L3 power planes).

4. **Major components instantiated in schematic (placeholders approved where needed):**

- ADAU1467 (U1), W25Q64JV (U2), CS8416 (U3 TEMP for AK4118), AK4458×2 (U4/U5), NB3L553 (U6), NSA3579D oscillator (U7 TEMP for NDK NZ2520SD), ESP32 module (U18), OPA1678×8 (U8–U15 TEMP for OPA1652), output connector (J3 placeholder).

5. **Digital-only connectivity created (no new passives added):**

- **I2S**: U3→U1 nets labeled **I2S_BCLK, I2S_LRCLK, I2S_DATA**.

- **SPI boot**: U2↔U1 nets labeled **SPI_CS, SPI_MOSI, SPI_SCK, SPI_MISO**.

- **Clock**: U7 OUTPUT→U6 ICLK net labeled **MCLK**; fanout to DSP/DACs created as **MCLK_DSP, MCLK_DAC1, MCLK_DAC2**.

- **TDM8**: U1→U4/U5 shared nets labeled **TDM_BCLK, TDM_LRCLK, TDM_DATA**.

- **I2C**: U18↔U1 nets labeled **I2C_SCL, I2C_SDA**, also connected to U3 SCL/SDA for optional SPDIF control.

### What still needs to be done to complete the project

#### Implementation plan (remaining work only)

1. **Normalize clock net naming to match requirement**

- Rename/merge **MCLK_DSP / MCLK_DAC1 / MCLK_DAC2** into a single net naming scheme that matches the requirement (**MCLK**) while preserving the fanout topology from NB3L553 outputs.

- Ensure the schematic clearly indicates the dedicated quiet clock corridor intent (annotation/net class later).

2. **Complete power distribution wiring (rails + grounding)**

- Wire and label rails: **VIN_12V, +5V_MAIN, +1V2_DSP_CORE, +3V3_DSP_DIG, +3V3_MCU, +3V3_DIG_AUDIO, +3V3_CLK, +5V_DAC_ANA, +12V_OPAMP** (and optional −12 V if included).

- Connect all IC power pins to the correct rails and connect all grounds to **^GND** (continuous L2 plane intent).

- Add ferrite-bead domain separation in the schematic once passive-add API is functional (or when allowed).

3. **Add required passives once schematic API issue is resolved**

- Add decoupling: **0.1 µF at every power pin** (DSP, DACs, CS8416, ESP32, oscillator, NB3L553) plus local bulk caps per rail.

- Add I2C pull-ups, reset/boot strapping components as required by ADAU1467/ESP32/CS8416.

4. **Wire the full analog signal chain (currently not connected)**

- Create consistent differential output net naming: **DACx_CHy_P / DACx_CHy_N** from AK4458 pins.

- Add per-channel RC reconstruction filters (100 Ω series + 2.2 nF to GND) between DAC outputs and op-amp inputs.

- Connect to OPA1678 buffers (TEMP), add 47–100 Ω output protection resistors, then connect to balanced board-to-board connector (J3) mapped for 16 differential channels + grounds.

5. **Schematic organization into functional blocks**

- Arrange/annotate sheets/blocks per zones: Power, Digital Input, DSP+Flash, Clock Island, DACs, Analog Output, MCU Control.

- Add notes that explicitly tie nets to routing corridors (Clock corridor, TDM corridor) and enforce “no digital through analog region”.

6. **Validation and handoff to layout**

- Run ERC and resolve actionable issues.

- Prepare for layout: assign net types/classes (Clock/TDM high priority; analog diff pairs), and ensure constraints are traceable in the schematic annotations.

### Known blockers / constraints

- Flux schematic edit API currently fails when adding generic passives (resistors/capacitors), so passives/decoupling/filters were deferred.

- Airwire DRC errors exist because the PCB is unrouted (expected at this stage); routing must be done later via Auto-Layout/manual routing.

- Temporary placeholders must remain clearly marked for later replacement:

- **CS8416-CSZ (U3)** → AK4118

- **NSA3579D (U7)** → NDK NZ2520SD 24.576 MHz

- **OPA1678IDR (U8–U15)** → OPA1652