Rev A — spec handoff + Objective 1 sourcing

flux

Final BOM completion is done with zero missing-MPN rows. J3 and BZ1 remain on PCB and are excluded from PCBA placement.
No Basic-class exact match was available for 1.78 kΩ, 3.01 kΩ, 90.9 kΩ, 3.48 kΩ, 178 kΩ, and 10 µF; Extended parts were assigned. Note: C14’s sourcing metadata is 0603, while its existing physical footprint remains 0805 because layout changes were prohibited.

  • sentry-node-v1-bom-jlcpcb.csv

    CommentDesignatorFootprintJLCPCB Part #LCSC Part #
    TMB12A03BZ1Through Hole D12mm P7.6mmC96222
    CL10A475KP8NNNCC1, C2, C3C1705
    GRM188R61A226ME15LC6, C7, C8C0603C167429
    CL10B104KB8NNNCC10, C11, C15, C16, C18, C20, C22, C25C_0603_1608MetricC1591
    CL10A106KP8NNNCC12, C4, C5, C9C19702
    CL10A105KB8NNNCC13, C17, C19, C21, C23C_0603_1608MetricC15849
    MMASL168BB5106MTNA01C14C_0603_1608MetricC6594205
    6SVPC330MC24CAP-SMD_BD6.3-L6.6-W6.6-FDC139569
    OCV101M0JTR-0606C26CAP-SMD_BD6.3-L6.6-W6.6-LS7.2-R-RDC134854
    USBLC6-2SC6D1C7519
    1N4148W-13-FD2, D3SOD-123_L2.7-W1.6-LS3.7-RDC112342
    BLM18AG601SN1DFB1C19330
    TYPE-C-31-M-12J1USB-C_SMD-TYPE-C-31-M-12C165948
    B2B-PH-SM4-TB(LF)(SN)J2CONN-SMD_B2B-PH-SM4-TB-LF-SNC160352
    XFL4020-152MECL1C3033018
    WS2812B-V6LED1SMD5050-4PC52917433
    ICS-43434M1, M2, M3, M4LGA-6 3.5x2.65mm bottom-portC5656610
    MMBT2222ALT1GQ1, Q2SOT-23C82460
    0603WAF5101T5ER1, R2R_0603_1608MetricC23186
    ERJ3EKF1781VR3R_0603_1608MetricC403029
    RC0603FR-073K01LR4R_0603_1608MetricC137732
    RC0603FR-0790K9LR5R_0603_1608MetricC185305
    CL0603FN3K48PR7R_0603_1608MetricC52209912
    ERJ-U03F1783VR10R_0603_1608MetricC1859202
    0603WAF1004T5ER11, R9R_0603_1608MetricC22935
    0603WAF1003T5ER12, R13, R8R_0603_1608MetricC25803
    0603WAF1002T5ER14, R6R_0603_1608MetricC25804
    0603WAF1001T5ER15, R16R_0603_1608MetricC21190
    0603WAF3300T5ER17R_0603_1608MetricC23138
    MK-12C02-G015S1SW-SMD_G-SWITCH_MK-12C02-G015C2911519
    K2-1114SA-A4SW-06SW2, SW3KEY-SMD_4P-L4.8-W4.6-P1.70-LS6.2C136662
    TS-1187A-B-A-BSW4SW-SMD_4P-L5.1-W5.1-P3.70-LS6.5-TL-2C318884
    BQ24074RGTRU1
    TPS63020DSJRU2C15483
    ESP32-S3-WROOM-1-N16R8U3WIRELM-SMD_ESP32-S3-WROOM-1C2913202
    Ra-01HU4WIRELM-SMD_RA-01HC503593

  • sentry-node-v1-pickplace-jlcpcb-corrected.csv

    DesignatorLayerRotationMid XMid Y
    C1Bottom028mm-4.5mm
    C2Bottom028mm-7.5mm
    C3Bottom036mm-6mm
    C4Bottom0-4mm4.7mm
    C5Bottom0-4mm-4.7mm
    C6Bottom03.8mm4.7mm
    C7Bottom03.8mm-4.7mm
    C8Bottom00.8mm-4.7mm
    C9Bottom0-18.5mm12mm
    C10Bottom0-4.8mm3.3mm
    C11Bottom034mm-1mm
    C12Bottom0-0.8mm4.7mm
    C13Bottom0-30.1mm10.4mm
    C14Bottom0-35.3mm10.4mm
    C15Bottom0-32.6mm10.4mm
    C16Bottom0-30.5mm-26.2mm
    C17Bottom0-30.5mm-29.8mm
    C18Bottom9030.5mm29.8mm
    C19Bottom030.5mm26.2mm
    C20Bottom90-30.5mm30mm
    C21Bottom0-25.5mm30mm
    C22Bottom9025.5mm-24.59mm
    C23Bottom9030.5mm-24.59mm
    C24Top0-13mm-27mm
    C25Top0-20mm0mm
    C26Top09mm22.5mm
    D1Bottom01mm-28mm
    D2Top0-22mm18mm
    D3Top0-31mm-6mm
    FB1Bottom0-14mm12mm
    J1Bottom00mm-36.9mm
    J2Bottom27037.44mm-25mm
    L1Bottom03.8mm0mm
    LED1Top00mm24mm
    M1Bottom0-28.327mm-28mm
    M2Bottom027.673mm28mm
    M3Bottom0-28.327mm28mm
    M4Bottom027.673mm-28mm
    Q1Top0-10mm18mm
    Q2Top0-31mm-12mm
    R1Bottom0-7mm-32mm
    R2Bottom0-7mm-35mm
    R3Bottom026mm-10mm
    R4Bottom029mm-10mm
    R5Bottom032mm-10mm
    R6Bottom035mm-10mm
    R7Bottom026mm-13mm
    R8Bottom029mm-13mm
    R9Bottom00mm-3.4mm
    R10Bottom04.8mm3mm
    R11Bottom09mm-8mm
    R12Bottom037mm-1mm
    R13Bottom034mm-3.5mm
    R14Bottom0-32.5mm11.6mm
    R15Top0-14mm15mm
    R16Top0-27mm-12mm
    R17Top029mm8mm
    S1Top18022.0254mm40.0435mm
    SW2Top0-11mm37mm
    SW3Top0-20mm37mm
    SW4Top00mm-26mm
    U1Bottom032mm-6mm
    U2Bottom0-2mm0mm
    U3Bottom270-32.87mm0mm
    U4Top18030.5mm-8mm
Details: Final BOM Completion Report. ORDER HELD — no order placed.
A

agamrossen

tell me exactly out of the display header pins which one is meant for which pin on the 1.54 inch waveshare e ink display

flux

The J3 display header is wired in the standard Waveshare 1.54-inch e-paper cable order:

Table

J3 pinBoard netWaveshare display pin
13V3_SYSVCC
2GNDGND
3SPI2_MOSIDIN
4SPI2_SCKCLK
5EPD_CSCS
6EPD_DCDC
7EPD_RSTRST
8EPD_BUSYBUSY
So the connection is 1→VCC, 2→GND, 3→DIN, 4→CLK, 5→CS, 6→DC, 7→RST, 8→BUSY.
This assumes pin 1 is identified from the PCB footprint’s pin-1 marker. Do not determine pin 1 solely by viewing the header from the cable side, because the apparent order reverses when viewed from the opposite face.
Verify display connector
Create firmware pin map
Review display power
Create bring-up checklist
Sign up to send

Files

Schematic

Layout

3D View

H4
H1
U3
M2
End of Life
BZ1
M3
End of Life
LED1
M1
End of Life
Q2
H2
H3
M4
End of Life
Q1
D1
SW4
R5
Resistance
90.9kΩ
R11
Resistance
1MΩ
R12
Resistance
100kΩ
R6
Resistance
10kΩ
R8
Resistance
100kΩ
R4
Resistance
3.01kΩ
R3
Resistance
1.78kΩ
R1
Resistance
5.1kΩ
R2
Resistance
5.1kΩ
R9
Resistance
1MΩ
R13
Resistance
100kΩ
R17
Resistance
330Ω
R15
Resistance
1kΩ
R16
Resistance
1kΩ
R14
Resistance
10kΩ
R10
Resistance
178kΩ
R7
Resistance
3.48kΩ
D3
FB1
SW3
C11
Capacitance
100nF
J2
C25
Capacitance
100nF
C15
Capacitance
100nF
C19
Capacitance
1uF
C27
Capacitance
100nF
C13
Capacitance
1uF
C21
Capacitance
1uF
C20
Capacitance
100nF
C23
Capacitance
1uF
C18
Capacitance
100nF
D2
SW2
C14
Capacitance
10uF
C10
Capacitance
100nF
C17
Capacitance
1uF
C22
Capacitance
100nF
C16
Capacitance
100nF
ANT1
C24
Capacitance
330uF
C2
Capacitance
4.7µF
TP2
TP15
J3
C4
Capacitance
10µF
TP5
U4
TP3
TP16
TP14
C1
Capacitance
4.7µF
C5
Capacitance
10µF
TP17
C9
Capacitance
10µF
TP6
TP12
TP9
TP7
TP13
C3
Capacitance
4.7µF
TP10
TP4
TP1
TP8
MP2
MP1
C12
Capacitance
10µF
TP11
U1
J1
C26
U2
C8
C7
S1
C6
L1
Inductance
1.5µH
Power Chain Design Notes
Frozen architecture
USB-C VBUS → BQ24074RGTR IN only. BQ24074 OUT is SYS_RAW, which is supplied from USB when present and from VBAT through the charger power path when USB is absent. SYS_RAW feeds TPS63020DSJR; the SS-12D00-G3 switches only the regulator EN logic. The charger therefore remains able to charge with the 3.3 V regulator off.
BQ24074 programming
  • USB posture: EN1 = high from USB_VBUS, EN2 = low, selecting datasheet USB500 mode (450 mA minimum, 475 mA typical, 500 mA maximum input-current limit).
  • Charge current: RISET = 1.78 kΩ, 1%. Using ICHG = KISET / RISET and KISET = 890 AΩ, ICHG = 890 / 1780 = 0.500 A nominal. The system load has priority; charge current automatically reduces when total USB current reaches the USB500 limit.
  • ILIM defined even though fixed USB500 mode is selected: RILIM = 3.48 kΩ. The programmable mode would be approximately 438 mA typical and 494 mA using maximum KILIM.
  • Termination: RITERM = 3.01 kΩ. Using ITERM = 0.030 × RITERM / RISET, the threshold is approximately 50.7 mA, near 10% of the 500 mA fast-charge target.
  • Timer: RTMR = 90.9 kΩ. Using the TI equation tMAXCHG = 10 × 48 s/kΩ × RTMR, the nominal fast-charge safety timeout is 43,632 s = 12.12 h. This meets the owner's ≥12 h budget for a ~3000 mAh cell that may receive only ~350 mA while the USB500 input is shared with the system load.
  • TS: fixed 10 kΩ directly from TS to GND, exactly as TI requires when no battery-pack thermistor is used.
  • CHG: open-drain CHG_STAT with 100 kΩ pull-up to 3V3_SYS, within TI's allowed 1 kΩ–100 kΩ range.
  • Bypass: Samsung CL10A475KP8NNNC, 4.7 µF, 10 V, X5R, 0603, LCSC C1705, on IN, OUT and BAT. The IN value remains below the USB hard-start 10 µF guidance.
TPS63020 3.3 V rail
  • TI Figure 25 / 1.5 A reference topology is used.
  • Feedback: Rtop = 1.00 MΩ, Rbottom = 178 kΩ. With VFB = 0.500 V, VOUT = 0.500 × (1 + 1,000/178) = 3.309 V nominal. This implements the owner's correction and meets the WS2812B-V6 datasheet minimum of 3.3 V nominal.
  • PS/SYNC is low, enabling power-save mode per TI. PG is unused and intentionally no-connected.
  • Enable: SS-12D00-G3 COM drives EN; NO connects to SYS_RAW. A 1 MΩ EN pulldown ensures shutdown when the switch is off or transitioning.
Power-stage parts

Table

FunctionSelected partLCSCVerified points
InductorCoilcraft XFL4020-152MECC30330181.5 µH ±20%; DCR 15.8 mΩ max; Isat 4.1/4.4/4.6 A for 10/20/30% drop; Irms 6.7 A at 20°C rise, 9.1 A at 40°C rise
Input MLCCs3× Samsung CL10A106KP8NNNCC1970210 µF, 10 V, X5R, 0603. Samsung DC-bias graph gives ≈4.2 µF each at 4.4 V, ≈12.6 µF total effective, above TI's ≥10 µF input recommendation
Output MLCCs3× Murata GRM188R61A226ME15LC16742922 µF, 10 V, X5R, 0603. Murata SimSurfing gives ≈15 µF each at 3.3 V, ≈45 µF total effective, above TI's ≈30 µF typical recommendation
VINA decoupling100 nF, 16 V, X7R, 0603commodityTI high-frequency control-stage bypass
Worst-case current check
Conservative battery-only input at the regulator is taken as 2.9 V: a 3.0 V depleted Li-Po minus the BQ24074 maximum 100 mV BAT-to-OUT drop at 1 A. For a 1 A, 3.3 V load and 85% assumed efficiency:
IIN(avg) = 3.3 V × 1 A / (2.9 V × 0.85) = 1.34 A.
For 1.5 µH and 2.4 MHz, boost duty is approximately (3.3−2.9)/3.3 = 0.121; the datasheet peak-current equation gives approximately 1.39 A steady-state peak. This is well below the selected inductor's 4.1 A conservative saturation point and 6.7 A 20°C-rise RMS rating. The TPS63020 datasheet also specifies more than 2 A output at 3.3 V for VIN >2.5 V, so the frozen ≥1 A continuous requirement has margin.
USB-alone operation remains source-limited to 500 mA by the BQ24074; if the enabled system demands more, DPPM reduces charging and the battery supplement path supplies the difference.
MIC_3V3 and sensing
  • Ferrite: Murata BLM18AG601SN1D, LCSC C19330, 600 Ω at 100 MHz, 500 mA rated, 0.8 Ω maximum DCR. At <10 mA microphone load, worst-case bead DC drop is <8 mV.
  • Filter capacitor: Samsung CL10A106KP8NNNC, 10 µF, 10 V, X5R, LCSC C19702, on the MIC_3V3 side.
  • Battery sense: 100 kΩ / 100 kΩ divider gives VBAT_SENSE = 0.5 × VBAT; 100 nF to GND gives a pole of about 1/(2π × (100k||100k) × 100nF) = 31.8 Hz.
Required named stubs
  • USB_DN
  • USB_DP
  • CHG_STAT
  • VBAT_SENSE
Schematic completion status
Objectives 3–5 were captured after the power-chain corrections: ESP32-S3-WROOM-1-N16R8 core and frozen GPIO map, four ICS-43434 microphones with per-mic bypassing and exact slot straps, alert outputs with approved WS2812B-V6/C52917433, the e-paper header, approved Ra-01H/C503593, and the specified test points. The executor's single final ERC retrieval reported no open warnings or errors; no second ERC pass was run, per owner instruction.
To preserve the explicit stop before layout, newly added Objective 3–5 components are currently marked schematic-only (Exclude from PCB). At the start of Objective 6, enable PCB inclusion before placement; this is a workflow state, not a BOM or architecture decision.

  • Frozen architecture

  • BQ24074 programming

  • TPS63020 3.3 V rail

  • Power-stage parts

  • Worst-case current check

  • MIC_3V3 and sensing

  • Required named stubs

  • Schematic completion status