I’ll research TI’s datasheet and authoritative sourcing information, then write the application guide with verified pin connections, design cautions, and clearly labeled alternatives.
I’ve verified the pinout and integration guidance, including the latch-off reset requirement and thermal-pad grounding. The alternative-part datasheet checks are still pending; I’ll distinguish manufacturer-confirmed functional alternatives from verified drop-in replacements.
The Texas Instruments TPS25940LRVCR is a programmable eFuse power-path protection IC with integrated back-to-back MOSFETs, current limiting, adjustable startup slew rate, and true reverse-current blocking. Its principal application is protecting SSD and other DC power rails, particularly systems with load-side hold-up energy that must not discharge into a failed input supply. TI product overview
1. Quick Specifications
Absolute maximum ratings are survival limits, not normal operating targets; they do not establish a permissible continuous operating point.
Specification discrepancy: TI's current product selector uses “0.6–5.2 A,” while the Rev. A datasheet headline uses “0.6–5.3 A.” Use the ele...
Created the TPS25940LRVCR Application and Usage Guide with all seven requested sections, TI datasheet citations, practical wiring guidance, layout cautions, and sourcing links. Alternatives are clearly labeled functional—not drop-in—with unresolved datasheet checks and distributor MOQ verification disclosed.
The Texas Instruments TPS25940LRVCR is a programmable eFuse power-path protection IC with integrated back-to-back MOSFETs, current limiting, adjustable startup slew rate, and true reverse-current blocking. Its principal application is protecting SSD and other DC power rails, particularly systems with load-side hold-up energy that must not discharge into a failed input supply. TI product overview
1. Quick Specifications
Absolute maximum ratings are survival limits, not normal operating targets; they do not establish a permissible continuous operating point.
IN: −0.3 to 20 V; 22 V permitted only for the specified 10 ms input transient.
Adjustable current limit
Datasheet headline: 0.6–5.3 A, ±8%; not an unconditional continuous-load rating.
No independent absolute-maximum continuous-current value was verified. Thermal design and current-limit tolerances govern usable current.
IN-to-OUT on resistance
42 mΩ typical; 49 mΩ maximum at TJ = 25°C; 64 mΩ maximum over −40 to 125°C, for IOUT = 1–5 A.
Not a voltage-regulator dropout specification.
Junction temperature, TJ
−40 to +125°C.
−40 to +150°C.
Storage temperature
Not an operating condition
−65 to +150°C.
OUT, PGTH, PGOOD, EN/UVLO, OVP, DEVSLP, FLT voltage
Keep within applicable recommended conditions, not merely absolute maximum
−0.3 to 20 V.
dVdT / ILIM voltage
Programming pins; do not drive as ordinary logic outputs
−0.3 to 3.6 V.
IMON voltage
Current-source monitoring output
−0.3 to 7 V.
Package
20-pin WQFN, RVC; 3 × 4 mm nominal body plus exposed thermal pad.
0.8 mm maximum package height; 0.5 mm terminal pitch.
Fault response
L version remains latched off after overload-induced thermal shutdown; cycle EN/UVLO low then high to reset.
Do not substitute auto-retry behavior in the system safety analysis.
Specification discrepancy: TI's current product selector uses “0.6–5.2 A,” while the Rev. A datasheet headline uses “0.6–5.3 A.” Use the electrical-characteristics limits for the selected resistor, not either headline, to determine protection margins. TI's ordering page also lists −40 to +85°C; the −40 to +125°C range above is explicitly the datasheet's junction-temperature range, not a claim about unrestricted ambient operation. TI ordering information
2. Pinout & Connections
Pin numbering and functions below are from TI's pin-function table; distinguish top-view numbering from a mirrored PCB view.
Table
Pin Number
Pin Name
Description
Best Practice
1
DEVSLP
Active-high DevSleep control
Tie to GND for normal operation when unused; high selects low-power mode.
2
PGOOD
Open-drain, active-high power-good indication
Add a pull-up when used. A 10 kΩ pull-up to the receiving logic supply is an engineering starting value, not a mandatory TI value; check sequencing and MCU tolerance. Leave open if unused.
3
PGTH
Positive input of power-good comparator
Feed from an OUT-to-GND divider if monitoring output voltage; rising threshold is 0.99 V typical. Tie to GND if unused.
4, 5, 6, 7, 8
OUT
Protected power output
Connect all five pins to the load-side power copper; do not use only one pad.
9, 10, 11, 12, 13
IN
Power input and IC supply
Connect all five pins to input copper; place local IN-to-GND bypass nearby.
14
EN/UVLO
Enable and programmable undervoltage lockout
Use a defined input-voltage divider or driven enable. Provide a means to pull low for latch reset; do not leave floating.
15
OVP
Programmable overvoltage cutoff input
Feed from an IN-to-GND divider; tie to GND when unused. This is cutoff, not output-voltage clamping.
16
GND
IC reference ground
Connect to quiet reference ground and the exposed pad.
17
ILIM
Current-limit programming
Resistor to quiet GND; place close to the pin. Never treat this as an enable input.
18
dVdT
Output ramp-rate programming
Capacitor to quiet GND for controlled startup. Choose value from required inrush and startup time.
19
IMON
Scaled output-current source
Resistor to GND converts current to voltage for an ADC; leave open when unused.
20
FLT
Active-low open-drain fault indication
Add a pull-up when used; 10 kΩ is a practical starting choice subject to logic and sink-current checks. Leave open if unused.
Exposed pad (often numbered 21 in CAD)
PowerPAD / GND
Electrical ground and heat-transfer pad
Solder to grounded copper and connect to a ground plane using multiple thermal vias; not NC.
PGTH rising threshold is 0.97/0.99/1.01 V min/typ/max. TI explicitly permits unused PGOOD and FLT to be left open or grounded, and requires their pull-ups to keep sink current at or below 10 mA. OVP grounding, DEVSLP held low, PGTH held low, and IMON open are supported by the unused-feature/test conditions; these are not interchangeable pin types. The exposed pad must connect to GND and a ground plane with multiple vias.
3. Standard Application Circuit
DC power-rail protection wiring
Use the IC in series between the DC source and load: source → all IN pins; all OUT pins → protected load. Join GND and the exposed pad to the ground system, and add the programming and monitoring components described below.
Input bypass: TI recommends a ceramic capacitor of 0.1 µF or greater from IN to GND. A 1 µF ceramic is a reasonable initial engineering choice, with voltage rating and effective capacitance checked at the actual bias. TI allows elimination or minimization in hot-plug applications with negligible input-path inductance; do not interpret that exception as permission to ignore transient testing.
Output capacitance: Size the load-side decoupling and bulk storage for the downstream load. No universal mandatory output-capacitor value was verified in this research. Include all downstream capacitance in startup analysis rather than copying a nominal test capacitor.
Current limit: Install R(ILIM) from ILIM to quiet ground. TI gives I(LIM) = 89 / R(ILIM), with current in amperes and resistor in kΩ. As a datasheet-grounded example, 20 kΩ produces 4.09/4.45/4.81 A min/typ/max, at VIN − VOUT = 1 V; these are pulse-tested electrical limits and thermal effects must be evaluated separately. Choose resistor tolerance and protection margin so legitimate load peaks stay below the minimum trip point while cables and loads tolerate the maximum.
Startup control: Install C(dVdT) from dVdT to GND. TI's ramp-time relation is t(dVdT) = 8.3 × 10^4 × VIN × C(dVdT); use seconds, volts and farads. For example, an engineering calculation at 12 V with 10 nF gives a nominal 9.96 ms ramp. This is illustrative, not a guaranteed startup time. Check capacitor tolerance, IC ramp variation, load behavior during startup, and transient dissipation. The basic capacitive-load relation is Iinrush = Cload × dVOUT/dt; add the load current already flowing during startup.
UVLO and OVP: Use separate IN-to-GND dividers if independent thresholds are desired. Both rising comparator thresholds are 0.97/0.99/1.01 V min/typ/max. For an independent divider, the nominal engineering relation is Vtrip = 0.99 V × (1 + Rtop/Rbottom). Include threshold spread, resistor tolerance and hysteresis; a shared three-resistor ladder needs its own coupled-divider calculation. Tie OVP to ground only when overvoltage cutoff is intentionally disabled.
Enable/reset: Provide a controlled pull-down of EN/UVLO, for example an open-drain controller output acting on the divider node, so firmware or supervisory logic can reset the L-version fault latch.
Power good: Use an OUT-to-GND divider into PGTH, then a pull-up on PGOOD to an appropriate logic rail. Verify that the chosen pull-up cannot expose an MCU input to the protected bus voltage.
Current monitor: IMON gain is 47.78/52.3/57.23 µA/A min/typ/max, specified for output currents from 1 to 5 A. Choose RIMON so maximum monitor current, resistor tolerance and ADC full-scale voltage remain compatible. Do not assume that this specified accuracy holds below 1 A.
This is an eFuse/load switch, not a buck converter or fixed-output LDO: normal OUT follows IN minus conduction loss. LED series-resistor, USB-C CC-resistor and connector-shielding instructions are not intrinsic to this component and are intentionally omitted.
4. PCB Layout & Routing Guidelines
High-current path: Connect every IN and OUT pin using short, broad copper. TI specifies power-path connections sized for at least twice full-load current. Determine actual width and via count from copper weight, permitted temperature rise, board stackup and fabrication limits; there is no universal trace width for this IC.
Thermal pad: Solder the exposed pad to GND copper and use multiple vias into the ground plane. As an assembly/thermal engineering practice, avoid narrow thermal-relief spokes that choke heat flow; coordinate via filling/tenting and stencil apertures with the assembler.
Decoupling loop: Place the input ceramic directly near IN and its ground return, minimizing loop area and inductance. Test real hot-plug and short-circuit transients; nominal VIN alone does not establish compliance with absolute maximum ratings.
Quiet programming ground: TI calls for a low-current SGND island/plane, joined to main power ground at the input-capacitor negative terminal. Put RILIM close to its pin, use the shortest return, and avoid coupling from switching signals. Keep the divider, ramp and monitor returns referenced to this quiet ground.
Signal routing: Keep control/sense traces away from high-current loops. There are no intrinsic high-speed differential pairs on this IC; USB/PCIe/SATA differential-pair rules apply to those separate interfaces, not to the eFuse pins.
5. Common Pitfalls / Things to Watch Out For
Treating the “5.3 A eFuse” headline as a continuous-current guarantee. Current-limit tolerance and PCB thermal performance are separate constraints. At 5 A, an engineering calculation using 42 mΩ typical gives 1.05 W conduction loss; using 64 mΩ maximum gives 1.60 W, before startup or fault dissipation. The resistor-set limit does not guarantee that a small copper footprint can carry that load continuously. Validate junction-temperature margin at worst ambient, real load and real copper geometry.
Assuming the L version automatically recovers after thermal overload. It remains latched off and needs an EN/UVLO reset; provide a controllable reset path instead of leaving enable floating or hard-wiring it beyond controller reach. Also remember that open-drain PGOOD/FLT cannot generate valid high levels without pull-ups, and bus-voltage pull-ups can damage low-voltage receiving logic.
6. Popular Alternatives & Equivalents
No cross-manufacturer drop-in replacement was verified. The following are manufacturer-confirmed functional alternatives, not procurement-approved substitutions; neither is claimed pin-compatible or footprint-compatible. Both are available in the Flux library.
Functionally similar only; not pin- or footprint-compatible.
ST identifies this as an electronic fuse for a 12 V line, with overcurrent protection, controlled output ramp and overvoltage clamping, rather than the TI part's programmable cutoff. Its manufacturer page identifies DFN10, 3 × 3 mm. Rework the footprint, current setting, enable/fault interface and voltage-protection behavior. Do not assume TI-equivalent reverse blocking, IMON or DevSleep. ST primary source
Functionally similar only; not pin- or footprint-compatible.
ADI describes an adjustable overvoltage, undervoltage and overcurrent power limiter with reverse-current and overtemperature protection; its product page identifies a 20-pin, 5 × 5 mm TQFN. Recheck operating range, fault response, startup behavior and external MOSFET requirements before selecting it. ADI primary source
Verification boundary: The alternative descriptions and package identities above are confirmed by manufacturer product pages. Both attempted alternative datasheet extractions remained pending after retry; detailed pin-map, electrical-limit and external-FET checks are therefore unresolved. Do not release a substitution on the basis of this table alone. “Popular” here denotes established functional options, not verified sales-volume rankings.
7. Sourcing & Purchasing Guide
Table
Attribute
Details
Primary Distributors
Buy directly from TI, or check listings at DigiKey, Mouser, and Arrow. A library-linked LCSC listing also exists; this guide does not independently establish its franchise status.
Packaging Options
TPS25940LRVCR: WQFN RVC, large tape-and-reel, 3,000 units standard package. TPS25940LRVCT: same device/package with 250-unit small tape-and-reel. TI describes full reel, cut tape and custom reel carrier options; exact offered options depend on the order. TI R packaging, TI T packaging
Standard MOQ
Verified standard reel quantities: 3,000 (R) and 250 (T). These are standard pack quantities, not a universal minimum order. A one-unit cut-tape MOQ could not be independently confirmed from a directly readable distributor page in this session; confirm it at checkout rather than assuming it.
Sourcing Advice
Confirm the L latch-off variant, RVC package, and final R/T carrier suffix on the purchase order. Use TI or manufacturer-authorized distributors with lot/date-code traceability; avoid unverifiable stock from non-authorized marketplaces. Confirm current stock, lead time, country-specific authorization and packaging before ordering. No live availability or price guarantee is made.
Research date: October 6, 2026. The project schematic, footprint and description were not changed or audited as part of this writing task.
Sources
Texas Instruments TPS25940x datasheet, SLVSCF3A, June 2014, revised March 2015; primary source for ratings, pinout, electrical characteristics, application equations and layout. Revision/date verified in the source.
TI TPS25940 product page, primary source for current product positioning and selector discrepancy.
Analog Devices MAX17525 product page, functional-alternative confirmation; the page lists datasheet Rev. 4, dated March 8, 2022. MAX17525 datasheet extraction remained pending; the page revision listing is not a substitute for a completed technical datasheet check.
Distributor links are purchasing destinations, not primary evidence for IC electrical limits. Flux library results confirmed the availability of the linked alternative component entries; their library metadata was not used as authority for electrical compatibility.