The 436-ball audit is still running because the mapping must be checked ball-by-ball against ST documentation; I’m keeping the physical pad mapping unchanged while that verification completes.

I’ve reconciled the completed correction with the live part: the old DDR_Ax terminals are gone and the CA/CKE/CS mappings are present. I’m doing the final clock-pair and 436-terminal integrity check now.

Fixed the STM32MP257FAI3 LPDDR4 pin naming issue. All 31 abstract DDR_Ax terminals were replaced with ST AN5723-aligned names for:

All 436 terminals remain present, BGA ball numbers and footprint mappings are unchanged, no DDR_Ax labels remain, and terminal review checks pass without errors or warnings. I also filed a part-quality report for engineering review.