ESP32 PoE+ W5500 Integration
- PoE PD: Implement 802.3af Class 3, bridge/EMI/TVS, isolated flyback to 5 V with TL431+opto and snubber.
- RJ45/Magnetics: Place MagJack; wire PoE pairs; route Ethernet pairs; add data-line ESD/CM choke.
- Secondary power: Filter 5 V; add buck 5 V→3.3 V; decouple and bead rails for ESP32/W5500.
- Integration: Place ESP32 + W5500; wire SPI/reset/clock/LEDs/straps; add decoupling and test points; mark isolation boundaries; compile BOM; run ERC/DRC.
- Target 3.3 V max current (for sizing the buck)?
- ESP32 as a module (e.g., module form factor) or bare SoC?
- PoE PD and isolation: add 802.3af PD controller + bridge/classification, EMI/TVS; design isolated flyback to regulated 5 V/1.5 A with TL431+opto and snubber.
- 3.3 V rail: add a 5 V→3.3 V buck rated ≥0.8 A with inductor and IO caps; per knowledge base guidance, place 100 nF at each VDD and a 10 µF bulk on the rail, and account for ESP32 transient peaks.
- Ethernet: place RJ45 with integrated magnetics; add data-line ESD and CM choke; connect W5500 MDI to magnetics.
- Integration and docs: wire ESP32↔W5500 (SPI/reset/strap/clock), add programming test points, compile the BOM, and run ERC/DRC.
Started implementing a plan
#Goal
- Design and add an IEEE 802.3af isolated PoE PD front-end that produces a regulated 5 V/1.5 A power supply, derive a local 3.3 V/0.8 A rail, and integrate an RJ45 connector with integrated magnetics to power and interface an ESP32 and W5500. Complete the design with a full schematic and BOM.
#Implementation plan
1. PoE PD and Isolation Front-End
1. Select and add an IEEE 802.3af PD controller and associated circuitry including classification and bridge functions.
2. Integrate EMI filtering components and TVS protection at the PoE input.
3. Design and add an isolated flyback converter using a transformer, optocoupler, TL431 feedback loop, snubber network, and secondary rectification to generate a regulated 5 V output at 1.5 A.
2. Secondary Rail (3.3 V) Derivation
1. Add filtering on the 5 V rail with bulk and decoupling capacitors as per design guidelines.
2. Select and integrate a 5 V to 3.3 V buck regulator capable of supplying at least 0.8 A peak current with appropriately sized inductors and input/output capacitors.
3. Place additional decoupling (100 nF per VDD and 10 µF bulk capacitor) for ESP32 and W5500 power stability.
3. Ethernet Interface with Integrated Magnetics
1. Place and configure an RJ45 connector with integrated magnetics.
2. Connect the PoE pairs to the PD front-end and route the data lines.
3. Add ESD protection and common-mode chokes on Ethernet signal lines.
4. MCU and Ethernet Controller Integration
1. Select and add an ESP32 (module form or bare chip based on project requirements) and a W5500 Ethernet controller.
2. Connect the ESP32 and W5500 using SPI and other necessary control signals; include reset, strap, and clock connections.
3. Integrate programming and test points for the ESP32 as per guidelines.
5. Documentation and Verification
1. Assign and verify designators for all components.
2. Compile a complete BOM with selected part numbers and manufacturers.
3. Run schematic ERC and layout DRC checks to ensure compliance with design requirements.
#Success criteria
- Achieve a stable 5 V/1.5 A output from the PoE PD front-end with proper isolation and safety features.
- Derive a stable 3.3 V/0.8 A rail that meets transient requirements for the ESP32 and W5500.
- Integrate a fully functional RJ45 with integrated magnetics ensuring proper PoE harvesting and Ethernet connectivity.
- A complete schematic and BOM that passes design rule checks and is ready for layout and fabrication.
