RK3566 Part Data Audit


Continued explicit metadata updates for the requested mux groups.
Updated this pass:
  • SDMMC1 pins: CLK, CMD, D0–D3, DET, PWREN
  • SDMMC2 mux pins across VOP_BT1120 and CIF alternate locations
  • CIF camera pins: CLKIN/CLKOUT, VSYNC, HREF, D8–D15, CAM_CLKOUT0/1
  • GMAC mux pins: RX/TX data/control, MDC/MDIO, clock/refclock muxes
  • SPI/UART/I2C mux pins on GPIO1/GPIO2 groups
Verified representative terminals from SDMMC1, SDMMC2, CIF, GMAC, UART, and SPI mux groups now show updated Pin Type, Pin Description, and Section values.
Continue with any remaining GPIO-only and miscellaneous mux terminals not covered yet.
I’ll finish the remaining GPIO-only and miscellaneous mux terminals, then spot-check a few updated pins.
Continued the remaining GPIO-only and miscellaneous mux terminal updates.
Updated this pass:
  • 32 kHz/reference clock mux terminals
  • PMIC sleep, TSADC shutdown, GPU power enable, flash voltage-select
  • SARADC VIN0–VIN3
  • GPIO-only pins
  • Remaining low-speed mux pins across I2C/SPI/PWM/I2S/GMAC/ISP/eDP/SATA activity LED functions
Verified representative GPIO/misc terminals now have updated Pin Type, Pin Description, and Section metadata.
Audit remaining terminals
Fix unspecified pins
Review part checks
Create pin report
Check footprint mapping

Name
Pin #
Type
Part Type
VSS_1
A1
Ground
Terminal
VSS_2
A2
Unspecified
Terminal
DDR4_CS1N/LPDDR4_CS1N_A/DDR3_CS1N/LPDD_R3_ODT1/AC26_
A3
Unspecified
Terminal
DDR4_CLKP/LPDDR4_CLKP_A/DDR3_CLKP/LPDD_R3_CLKP/AC23
A5
Unspecified
Terminal
DDR4_A0/LPDDR4_CLKP_B/DDR3_A9/-/AC0_
A7
Output
Terminal
DDR4_A13/LPDDR4_A0_B/DDR3_A14/LPDDR3_A_0/AC13
A9
Output
Terminal
DDR4_A7/LPDDR4_ODT0_CA_B/DDR3_A8/-/AC7
A10
Unspecified
Terminal
DDR_DQS0N_B/DDR4_DQSU_N_B/LPDDR4_DQS_0N_B/DDR3_DQS2N/LPDDR3_DQS0N
A12
Unspecified
Terminal
DDR_DQS0P_B/DDR4_DQSU_P_B/LPDDR4_DQS0_P_B/DDR3_DQS2P/LPDDR3_DQS0P_
A13
Bi-Directional
Terminal
DDR_DQ12_B/DDR4_DQL7_B/LPDDR4_DQ12_B/_DDR3_DQ28/LPDDR3_DQ16
A15
Bi-Directional
Terminal
DDR_DQS1P_B/DDR4_DQSL_P_B/LPDDR4_DQS1_P_B/DDR3_DQS3P/LPDDR3_DQS2P
A17
Unspecified
Terminal
DDR_DQ9_B/DDR4_DQL2_B/LPDDR4_DQ9_B/DD_R3_DQ25/LPDDR3_DQ19
A19
Bi-Directional
Terminal
DDR_DQ10_B/DDR4_DQL4_B/LPDDR4_DQ10_B/_DDR3_DQ26/LPDDR3_DQ22
A20
Bi-Directional
Terminal
I2C3_SDA_M0/UART3_RX_M0/AUDIOPWM_LOUT__P/GPIO1_A0_U
A22
Bi-Directional
Terminal
I2S1_MCLK_M0/UART3_RTSN_M0/SCR_CLK/GPIO_1_A2_D
A23
Output
Terminal
I2S1_SDO2_M0/I2S1_SDI2_M0/PDM_SDI2_M0/P_CIE20_WAKEN_M2/GPIO1_B1_D
A26
Bi-Directional
Terminal
EMMC_CMD/FLASH_WRN/GPIO1_C4_U_
A27
Bi-Directional
Terminal
EMMC_CLKOUT/FLASH_DQS/GPIO1_C5_D
A29
Output
Terminal
EMMC_D5/FLASH_D5/GPIO1_C1_U_
A30
Bi-Directional
Terminal
EMMC_D0/FLASH_D0/GPIO1_B4_U_
A32
Bi-Directional
Terminal
EMMC_D7/FLASH_D7/GPIO1_C3_U
A33
Bi-Directional
Terminal
SDMMC1_PWREN/I2C4_SDA_M1/UART8_RTSN_M_0/GPIO2_B1_D_
A35
Output
Terminal
I2S2_LRCK_RX_M0/UART6_CTSN_M0/SPI1_CS0__M0/GPIO2_C0_D
A37
Bi-Directional
Terminal

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