The Renesas RAA2361052GNP#HC5 is an integrated synchronous buck-boost DC/DC regulator with resistor-coded output-voltage and input-current-limit settings, intended to maintain a battery-powered rail as the battery voltage crosses the output voltage. Its common application is a low-standby-power sensor or portable system powered from a single-cell lithium-ion battery or a multi-cell alkaline battery pack, using the reference power stage described below. Renesas product overview
Lifecycle warning: Renesas currently lists RAA236105 as Not Recommended for New Designs (NRND) and points to ISL9122A as an alternative; that recommendation does not establish drop-in compatibility. Renesas lifecycle notice
1. Quick Specifications
Absolute maximum ratings are stress limits, not permissible continuous operating targets. All voltages below are relative to GND.
Exposed ground pad is additional to the ten numbered leads, explaining an 11-pad CAD footprint.
2. Pinout & Connections
Pin assignments and mandatory no-floating requirements are from datasheet Table 2. Practical routing recommendations are identified as engineering guidance where not directly specified.
Table
Pin Number
Pin Name
Description
Best Practice
1
EN
Active-high enable
Never float. Drive with defined logic; meet high ≥1.45 V and low ≤0.4 V. For the always-on example, tie to VIN.
2
RSVD
Reserved
Pull down/tie to GND; never leave open.
3
BYPASS
Active-high forced-bypass control
Tie to GND for normal regulation. Never float. Assert only when the load may accept an unregulated battery-following rail.
4
ILIM
Resistor reader for input current limit
Connect the decoded resistor to GND. For the 3.3 V example, 0 Ω disables the selectable input limit.
5
VSET
Resistor reader for output-voltage target
For 3.3 V with ILIM = 0 Ω, connect 332 kΩ, 1%, to GND. Not a conventional feedback divider.
6
VOUT
Converter output
Connect to load and local ceramic COUT to GND; maintain ≥6 µF effective capacitance.
7
LX2
Output-side/boost switch node
Connect to one end of the inductor; keep switching copper compact (engineering guidance).
8
GND
Main controller ground
Connect to ground plane and capacitor/resistor ground returns.
9
LX1
Input-side/buck switch node
Connect to the other end of the inductor; do not connect the inductor directly to VIN.
10
VIN
Input supply
Connect to battery and local CIN to GND; maintain ≥5 µF effective capacitance.
EPAD
EPAD
Exposed thermal/ground pad
Must be soldered and connected to PCB ground, not left electrically or mechanically unsupported.
3. Standard Application Circuit
3.3 V battery-powered buck-boost regulator
Use the following explicit net connections for a continuously enabled, normally regulated rail:
Battery positive → VIN (10) and EN (1); battery negative → GND (8) and EPAD. This always-on EN tie is engineering guidance for a battery constrained to the recommended VIN range, not a requirement for MCU-controlled operation.
1 µH inductor between LX1 (9) and LX2 (7); 10 µF ceramic CIN between VIN and GND. These values are verified in the Figure 2 application evidence.
22 µF ceramic COUT between VOUT (6) and GND is a supported starting choice from the recommended-output-capacitor table, not a claim that the Figure 2 output-capacitor label was conclusively extracted. The verified table includes 22 µF, 10 V, 0603 Murata GRM188R61A226ME15D.
RSVD (2) → GND; BYPASS (3) → GND for regulation.
VSET (5) → 332 kΩ, 1% → GND; ILIM (4) → 0 Ω → GND. This selects 3.3 V with selectable input current limiting disabled.
Passive selection: Use X5R or X7R output MLCCs and check capacitance loss from DC bias and temperature. Nominal 10 µF CIN and 22 µF COUT must still meet the 5 µF input and 6 µF output effective minima in the finished design. A 10 V voltage rating is a practical starting preference, not a universal substitute for checking the manufacturer's bias curves.
The datasheet recommends 1 µH Murata DFE18SBN1R0ME0 and DFE18SAN1R0MG0, with typical DCR of 100 mΩ and 107 mΩ respectively. Avoid saturation under worst-case operating conditions and minimize DCR/core loss; do not choose an inductor solely because its current rating equals the DC load current. Exact acceptable saturation-current margin for a substituted inductor remains a design-specific check; it is not established here.
Choosing a limited-input-power setting
For a 3.3 V target, keep VSET at 332 kΩ and choose the following ILIM-to-GND values from the lower resistor-code bank.
Table
ILIM resistor
Decoded input-current limit
0 Ω
Disabled
3.01 kΩ
1 mA
6.81 kΩ
2 mA
11.5 kΩ
5 mA
17.4 kΩ
10 mA
24.9 kΩ
20 mA
34.0 kΩ
50 mA
Use the specified E96, 1% pin-reader resistors. ILIM and VSET are read once during startup; changing their resistance during operation does not change the selected output or limit. Changing ILIM to the upper code bank also changes the output-voltage range decoded with VSET: consult both Tables 3 and 4 rather than treating the two settings as independent.
The selectable limit constrains input current, not output current. As an engineering power-budget estimate, available output power cannot exceed efficiency times available input power; a low input-current setting cannot sustain the headline full-load output.
Variant distinction: RAA236105 current-limit variant does not support DVS; datasheet Section 5.2 explicitly states this. Do not copy the RAA236100 I²C or VSEL configuration into this design.
4. PCB Layout & Routing Guidelines
The reviewed datasheet does not provide a dedicated detailed layout section or numeric trace-width/thermal-via prescription. The first two requirements below are source-backed; the remaining recommendations are general switching-converter engineering guidance, not Renesas-specific numeric rules.
Decoupling: Place CIN immediately beside VIN and its ground return. Add bulk capacitance nearer the source when long battery wires are present to damp startup ringing/overshoot. Place COUT close to VOUT and GND as engineering guidance to minimize the output pulsed-current loop.
Thermal grounding: Solder EPAD and connect it to PCB GND. Use low-impedance ground copper and suitable thermal vias where the stackup and assembly process permit. Avoid narrow thermal-relief spokes in the high-frequency capacitor-return path; thermal-relief geometry and via count are design decisions, not verified datasheet prescriptions.
Switch nodes: Place the inductor adjacent to LX1/LX2 and minimize loop length and switching-node area. Keep ILIM/VSET traces away from switching copper, with their ground returns referenced to a quiet local ground region. Do not create oversized LX pours for heat spreading.
Power copper: Use short, wide VIN/VOUT/ground paths sized for worst-case input current, switching/inductor current, copper thickness, allowable temperature rise, and voltage drop—not merely the nominal output current. No universal trace width is asserted without a stackup and current budget.
Routing applicability: LX1 and LX2 are not a differential signal pair; impedance-controlled differential-pair routing is not applicable to this regulator. Validate the DFN land pattern, exposed pad, paste apertures, and pin-1 orientation against the manufacturer package drawing before fabrication; equal body size/pitch alone does not prove footprint compatibility.
5. Common Pitfalls / Things to Watch Out For
Misprogramming or leaving controls floating. EN, BYPASS, RSVD, ILIM, and VSET need defined connections. VSET is a startup resistor code rather than a feedback-divider node, and its output mapping depends on the ILIM code bank. Do not assume I²C or runtime DVS is available on this variant.
Designing to headline values instead of worst-case operation. 400 mA is not guaranteed at every VIN/VOUT combination; the 1.8 V-to-5.0 V case has an 86.4 mA minimum maximum-load specification. A nominal MLCC that derates below CIN = 5 µF or COUT = 6 µF does not meet the recommended conditions. Solder EPAD to ground and assess heating under the actual load.
6. Popular Alternatives & Equivalents
No verified drop-in replacement was established. The two other-manufacturer options below are functionally similar regulators, not automatic BOM substitutions. Recheck startup, shutdown isolation, bypass behavior, passive values, output setting, maximum load, footprint, and supply-chain status before replacing the device.
Ultra-low-IQ buck-boost option. TPS63900 specifies 0.4 A maximum recommended output current at VIN ≥2.0 V, VOUT = 3.6 V. IQ is 75 nA typical, 1 µA maximum with EN = 3 V, no load, not switching, and unlimited-current setting.
Functionally similar; not pin-compatible. Same nominal 2.5 × 2.5 mm, 0.5 mm pitch package scale, but pins 2–5 are SEL/CFG1/CFG2/CFG3 rather than RSVD/BYPASS/ILIM/VSET. Full land-pattern compatibility was not verified; requires control-network redesign.
ADI's primary product page identifies LTC3531 as a battery-oriented synchronous buck-boost family with fixed 3.3 V versions and ThinSOT packaging. ADI product sourceDatasheet evidence extraction remains pending, so this is a manufacturer-product-page-confirmed functional candidate, not a completed datasheet-qualified substitute.
Functionally similar only; not pin-compatible or footprint-compatible with the ten-lead DFN device. The library identifies this ordering code as six-terminal TSOT-23-6. It cannot be assumed to meet a 400 mA requirement; full load/IQ/bypass qualification remains open. Library lifecycle metadata reports restricted availability, so confirm supply before selecting it for shortage mitigation.
Additionally, Renesas names ISL9122A as its migration recommendation on the RAA236105 product page. This is a same-manufacturer migration lead, not one of the two cross-manufacturer equivalents above, and pin/footprint compatibility has not been established. Renesas recommendation
7. Sourcing & Purchasing Guide
Table
Attribute
Details
Primary Distributors
Renesas's exact-MPN page lists Mouser, DigiKey, Avnet, and Newark as distributor channels. Listing is not a guarantee of stock. Manufacturer purchasing page
Packaging Options
The exact RAA2361052GNP#HC5 ordering code is listed by Renesas with Reel carrier type. Distributor cut-tape or re-reel availability for this exact code was not verified; request it explicitly rather than assume it. Manufacturer ordering-code details
Standard MOQ
Manufacturer-listed MOQ: 6,000 units. A one-unit cut-tape MOQ and the number of units per physical reel were not independently verified; do not equate the MOQ to a confirmed reel count. Manufacturer ordering-code details
JLCPCB / LCSC planning
JLCPCB has an exact-code listing, C42137380, but that listing is not proof of assembly stock, correct library geometry, or distributor authorization. Confirm stock, procurement eligibility, and package data before committing a JLCPCB assembly BOM. JLCPCB part listing
Sourcing Advice
Prefer manufacturer-listed franchised channels. Preserve the full ordering code, including 2GNP#HC5; verify package, carrier, lot/date code, and documentation on the quote. Do not infer counterfeit-free provenance from independent-marketplace stock claims. Since this family is NRND, obtain lifecycle/last-time-buy guidance and qualify a redesign alternative before committing production. Lifecycle source
Assembly handling
Renesas lists this ordering code as MSL 3, lead-free. Obtain the current storage, floor-life, baking, and reflow instructions from the supplied packaging documents before assembly. Manufacturer exact-part page
Verification boundaries: The exact Figure 2 COUT label could not be conclusively validated; the 22 µF starting value above is grounded instead in the recommended capacitor table. Distributor cut-tape MOQ, live stock, full reel quantity, numeric PCB trace widths, detailed thermal-via geometry, and drop-in replacement availability were not verified. LTC3531 datasheet indexing remained pending after retry; its detailed substitution qualification is still open. No schematic, footprint, or PCB was modified for this guide.
Sources
Renesas, RAA236100, RAA236105 Datasheet — revision 1.03, January 24, 2025; pin Table 2, Section 3 specifications, Section 5.2/Tables 3–4 resistor decoding, Section 7 passive selection, and ordering/revision tables. Manufacturer datasheet. Revision/date verified from the revision table.
Renesas, RAA236105 product page — lifecycle notice and recommended migration lead; web page, no revision/date stated. Primary source.
Renesas, RAA2361052GNP#HC5 exact-part page — package dimensions, pitch, carrier, MOQ, MSL, and distributor channels; web page, no revision/date stated. Primary source.
Texas Instruments, TPS63900 Datasheet — pin-function table, recommended operating conditions, electrical characteristics, and package drawing. Document revision/date was not extracted in this review. Manufacturer datasheet.
Analog Devices, LTC3531 product page — functional candidate confirmation. Primary source. Manufacturer datasheet was located, but citation-backed extraction remained pending; its revision/date was not verified.
JLCPCB, C42137380 exact-part listing — assembly-channel listing only; not used as an electrical-specification authority. Listing.
Research performed October 7, 2026. Dynamic lifecycle, stock, MOQ, and packaging information should be reconfirmed at purchase time.