Part Datasheet Review and Mismatch Check

flux

I’ll populate terminal metadata from the existing ball names: grouping pins by LPDDR channel/function, adding concise datasheet-style descriptions, section labels, and symbol orientation consistently across all 200 terminals.

flux

Signal metadata is populated for the data, strobe, command/address, clock, control, power, ground, reserved, and calibration groups. I’m doing a quick coverage check now.

flux

Completed the metadata population pass for the 200-terminal LPDDR4/LPDDR4X part.
Updated:
  • Pin Description
  • Pin Group
  • Pin Orientation
  • Section
Coverage included:
  • DQ data pins
  • DMI pins
  • DQS true/complement strobes
  • CA command/address pins
  • CK true/complement clocks
  • CKE, CS, ODT_CA, RESET_n control pins
  • VDD1, VDD2, VDDQ power pins
  • VSS ground pins
  • ZQ calibration pins
  • NC and DNU reserved/no-connect pins
I also preserved the earlier caution that VS appears likely intended to be VSS, but left the designator unchanged and marked it as a ground-related review item rather than silently renaming it.
Fix VS pin
Verify metadata coverage
Cross-check ball map
Review ERC now
Add high-speed attributes
Sign up to send

Files

Pins

Symbol

Layout

3D View

VDD1
Pin Number
T9
VSS
Pin Number
A3
VDDQ
Pin Number
B3
ZQ0
Pin Number
A5
DNU
Pin Number
A2
DMI0_A
Pin Number
C3
DQ0_A
Pin Number
B2
CS1_B
Pin Number
R3
CS0_B
Pin Number
R4
VDD2
Pin Number
R5
VDD1
Pin Number
U1
ZQ1
Pin Number
A8
VSS
Pin Number
T5
DQ7_A
Pin Number
B4
DQ15_A
Pin Number
B9
DNU
Pin Number
B1
VDD1
Pin Number
T4
VDD2
Pin Number
A9
VSS
Pin Number
T1
ODT_CA_B
Pin Number
T2
CA0_B
Pin Number
R2
VDD2
Pin Number
R8
DQ1_A
Pin Number
C2
VSS
Pin Number
C1
DQ3_B
Pin Number
U2
DNU
Pin Number
A1
CA2_B
Pin Number
R9
VDDQ
Pin Number
B8
VSS
Pin Number
T3
VDD2
Pin Number
R1
VSS
Pin Number
T8
VDDQ
Pin Number
B5
VDD2
Pin Number
A4
CK_c_B
Pin Number
P9
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
DNU
A1
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_1_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
DNU
A2
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_1_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
VSS
A3
Power Out
Ground
Ground
Bottom
80
MT53E1536M32D4DT-046_WT_A_1_1
Ground reference / return connection for core and I/O supplies.
VDD2
A4
Power In
Power
Power
Top
10
MT53E1536M32D4DT-046_WT_A_1_1
Core supply rail input; nominal 1.1 V for LPDDR4/LPDDR4X operation.
ZQ0
A5
Power In
Analog
Reference
Right
70
MT53E1536M32D4DT-046_WT_A_1_1
Channel A impedance calibration reference; connect to external precision ZQ resistor per Micron application guidance.
ZQ1
A8
Power In
Analog
Reference
Right
70
MT53E1536M32D4DT-046_WT_A_1_1
Channel B impedance calibration reference; connect to external precision ZQ resistor per Micron application guidance.
VDD2
A9
Power In
Power
Power
Top
10
MT53E1536M32D4DT-046_WT_A_1_1
Core supply rail input; nominal 1.1 V for LPDDR4/LPDDR4X operation.
VSS
A10
Power Out
Ground
Ground
Bottom
80
MT53E1536M32D4DT-046_WT_A_2_1
Ground reference / return connection for core and I/O supplies.
DNU
A11
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_2_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
DNU
A12
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_2_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
DNU
AA1
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_2_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
DQ0_B
AA2
Bi-Directional
Data
Data Bus
Left
50
MT53E1536M32D4DT-046_WT_A_2_1
Channel B data I/O bit 0.
VDDQ
AA3
Power In
Power
Power
Top
10
MT53E1536M32D4DT-046_WT_A_2_1
I/O supply rail input; nominal 1.1 V for LPDDR4 or 0.6 V for LPDDR4X operation.
DQ7_B
AA4
Bi-Directional
Data
Data Bus
Left
50
MT53E1536M32D4DT-046_WT_A_2_1
Channel B data I/O bit 7.
VDDQ
AA5
Power In
Power
Power
Top
10
MT53E1536M32D4DT-046_WT_A_2_1
I/O supply rail input; nominal 1.1 V for LPDDR4 or 0.6 V for LPDDR4X operation.
VDDQ
AA8
Power In
Power
Power
Top
10
MT53E1536M32D4DT-046_WT_A_2_1
I/O supply rail input; nominal 1.1 V for LPDDR4 or 0.6 V for LPDDR4X operation.
DQ15_B
AA9
Bi-Directional
Data
Data Bus
Left
50
MT53E1536M32D4DT-046_WT_A_2_1
Channel B data I/O bit 15.
VDDQ
AA10
Power In
Power
Power
Top
10
MT53E1536M32D4DT-046_WT_A_2_1
I/O supply rail input; nominal 1.1 V for LPDDR4 or 0.6 V for LPDDR4X operation.
DQ8_B
AA11
Bi-Directional
Data
Data Bus
Left
50
MT53E1536M32D4DT-046_WT_A_2_1
Channel B data I/O bit 8.
DNU
AA12
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_2_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
DNU
AB1
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_2_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
DNU
AB2
Not Connected
MISC
MISC
Right
60
MT53E1536M32D4DT-046_WT_A_2_1
Do Not Use ball; leave unconnected unless explicitly directed by Micron documentation.
VSS
AB3
Power Out
Ground
Ground
Bottom
80
MT53E1536M32D4DT-046_WT_A_2_1
Ground reference / return connection for core and I/O supplies.

MT53E1536M32D4DT-046 WT:A