Part Metadata Review and Verification
Thought for 1 min 12 sec
Part review result
1) Available part information
2) Datasheet URL status
3) Datasheet metadata summary
4) Absolute maximum ratings
5) Recommended operating conditions / key electrical characteristics
6) Pin descriptions
7) Package dimensions from datasheet
8) Cross-check: symbol and footprint vs datasheet
9) Issues flagged
Bottom line
Table
| Field | Result |
|---|---|
| MPN | MCP2518FDT-E/SL |
| Manufacturer | Microchip |
| Description | Stand-alone low-power CAN FD controller with SPI interface |
| Part type | Integrated Circuits |
| Datasheet URL in project | Present |
| Package implied by MPN suffix | SL = 14-lead narrow SOIC, 3.90 mm body |
| Footprint asset in project | SOIC127P600X175-14N.kicad_mod |
| 3D model in project | Present (.stp) |
| Pin count in symbol | 14 |
| Pin count in footprint | 14 pads |
| Nets in part project | None defined |
Table
| Check | Result |
|---|---|
| Datasheet property needed to be added? | No |
| Reason | A datasheet URL is already set on the part project, so step 2 was not needed. |
Table
| Category | Summary |
|---|---|
| Device function | External CAN FD controller with SPI interface; supports Classical CAN 2.0B and CAN FD per ISO 11898-1:2015 |
| Voltage range | 2.7 V to 5.5 V |
| Active supply current | 15 mA typ, 20 mA max at 40 MHz SYSCLK with 20 MHz SPI activity |
| Sleep current | 15 µA typ, 60 µA max at up to +85 °C; 600 µA max at up to +150 °C |
| Low-power mode current | 4 µA typ, 10 µA max |
| SPI speed | Up to 20 MHz |
| CAN speeds | Arbitration up to 1 Mbps, data phase up to 8 Mbps |
| Oscillator support | 4 / 20 / 40 MHz crystal, resonator, or external clock |
| Temperature grades | E: -40 °C to +125 °C, H: -40 °C to +150 °C |
| Memory / message handling | 2 KB RAM, 31 FIFOs, 1 TXQ, 1 TEF, 32 filter/mask objects |
| Extra features | ECC-protected RAM, SPI CRC support, timestamping, up to 3 interrupt pins, GPIO capability, standby control, CLKO/SOF output |
Table
| Parameter | Rating |
|---|---|
| VDD | -0.3 V to 6.0 V |
| DC voltage on all I/O relative to GND | -0.3 V to VDD + 0.3 V |
| Virtual junction temperature | -40 °C to +165 °C |
| Lead soldering temperature, 10 s | +300 °C |
| ESD, HBM | ±4 kV |
| ESD, MM | ±400 V |
| ESD, CDM | ±750 V |
Table
| Parameter | Value |
|---|---|
| Supply voltage VDD | 2.7 V to 5.5 V |
| POR release threshold VPORH | 2.65 V max |
| POR assert threshold VPORL | 2.2 V min |
| VDD rise rate for POR | 0.05 V/ms min |
| Input high VIH | 0.7 × VDD min |
| Input low VIL | 0.3 × VDD max |
| Output high VOH | VDD - 0.7 V min for TXCAN at -8 mA; VDD - 0.6 V min for others at -2 mA |
| Output low VOL | 0.6 V max |
| External digital clock on OSC1 | 2 MHz to 40 MHz |
| Crystal/resonator options | 4 MHz ±0.5%, 20 MHz ±0.5%, 40 MHz ±0.5% |
| Oscillator startup | 3 ms max from POR and from Sleep |
Table
| Pin | Symbol terminal in project | Datasheet function | Match |
|---|---|---|---|
| 1 | TXCAN | Transmit output to CAN FD transceiver | Yes |
| 2 | RXCAN | Receive input from CAN FD transceiver | Yes |
| 3 | CLKO/SOF | Clock output / Start-of-Frame output | Yes |
| 4 | ~{INT} | Interrupt output, active low | Yes |
| 5 | OSC2 | External oscillator output | Yes |
| 6 | OSC1 | External oscillator input | Yes |
| 7 | VSS | Ground | Yes |
| 8 | ~{INT1}/GPIO1 | RX interrupt output / GPIO | Yes |
| 9 | ~{INT0}/GPIO0/XSTBY | TX interrupt output / GPIO / Transceiver standby | Yes |
| 10 | SCK | SPI clock input | Yes |
| 11 | SDI | SPI data input | Yes |
| 12 | SDO | SPI data output | Yes |
| 13 | NCS | SPI chip select input (nCS) | Yes |
| 14 | VDD | Positive supply | Yes |
Table
| Parameter | Datasheet |
|---|---|
| Package | 14-lead plastic SOIC, narrow |
| Body length D | 8.65 mm BSC |
| Body width E1 | 3.90 mm BSC |
| Overall width E | 6.00 mm BSC |
| Pitch e | 1.27 mm BSC |
| Overall height A | 1.75 mm max |
| Lead width b | 0.31 mm to 0.51 mm |
| Lead thickness c | 0.10 mm to 0.25 mm |
| Lead length L | 0.40 mm to 1.27 mm |
| Recommended land pad length Y | 1.55 mm nominal |
| Recommended land pad width X | 0.60 mm nominal |
| Recommended row spacing | 5.40 mm nominal |
Table
| Check | Observed in project | Datasheet | Result |
|---|---|---|---|
| Package family | SOIC footprint file name indicates SOIC127P600X175-14N | SL = 14-lead SOIC | Match |
| Pin count | 14 symbol terminals / 14 footprint pads | 14 pins | Match |
| Pin numbering | Pads 1-14 present | Pins 1-14 | Match |
| Pin names | Symbol names align to datasheet naming/function | Datasheet pinout | Match |
| Pad pitch | 1.27 mm from footprint asset | 1.27 mm BSC | Match |
| Row spacing | Pad centers at ±2.7 mm, giving 5.40 mm | 5.40 mm nominal | Match |
| Pad size | 0.65 mm × 1.50 mm in footprint asset | 0.60 mm × 1.55 mm nominal | Close / acceptable |
| Package height encoded in footprint name | 1.75 mm | 1.75 mm max | Match |
| Exposed pad handling | No EP in footprint | SOIC SL package has no EP | Match |
| 3D model presence | Present | Optional but useful | Good |
Table
| Severity | Finding | Risk |
|---|---|---|
| Low | All symbol terminals are currently typed as Passive rather than input/output/power/ground classifications | Not a manufacturing problem, but can reduce ERC quality when this part is used in designs |
| Low | Project property says Part Type: Integrated Circuits while description says CAN Interface IC | Metadata consistency only; no board-failure risk |
| None found | No symbol-to-datasheet pin mismatch detected | No immediate functional risk |
| None found | No footprint/package mismatch detected for MCP2518FDT-E/SL | No immediate ordering/manufacturing risk |
| None found | No missing exposed pad issue, because /SL is SOIC, not VDFN | No assembly risk |
Table
| Verdict | Result |
|---|---|
| Ordering risk | No critical mismatch found |
| Manufacturing risk | No critical mismatch found |
| Functional risk from symbol/footprint mapping | No critical mismatch found |
| Recommended cleanup | Improve terminal electrical types for better ERC behavior |
If you want, I can next turn this into a clean part QA checklist or a datasheet-derived pin/property update list for the part project.
@review ERC/DRC check
Fix pin types
Check BOM metadata
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