Part Audit and Datasheet Review

flux

Completed the audit and set the official Analog Devices datasheet URL: https://www.analog.com/media/en/technical-documentation/data-sheets/ltm4712.pdf
Summary:
  • Symbol: 144 terminals match the datasheet 144-ball assignment.
  • Footprint: 144 pads match the CSP_BGA ball count.
  • Key flags: project name uses LTM4712IY-PBF while the official order code is LTM4712IY#PBF; pin descriptions are mostly missing; several pin types should be refined, especially INTVCC, VOUT, and SW1/SW2.
  • Footprint pitch/pad/body dimensions should be spot-checked against the datasheet mechanical drawing before release.
I saved the detailed report here: Part Audit: LTM4712IY#PBF
A

adrian95

Fix the MPN formatting and missing pin descriptions from the datasheet. Also please convert the symbol to parametric style, and place each pin into the correct section based on the datasheet. also add pin group and pin orientation for all the pins.

flux

I’ll update the official MPN formatting, add datasheet-derived pin descriptions, and restructure the symbol metadata into parametric sections/groups with orientations and ordering.

flux

The official MPN/project name and all unique signal/power-control pins are updated. I’m applying the repeated power/ground ball metadata next, which is the bulk of the 144-ball symbol.

flux

Done.
  • Renamed the project to the official MPN format: LTM4712IY#PBF.
  • Converted the symbol terminals to Parametric style.
  • Added datasheet-derived Pin Description, Section, Pin Group, Pin Orientation, and Terminal Order metadata across the 144-ball symbol.
  • Refined key pin types, including INTVCC as power output, VOUT as power output, and SW1/SW2 as passive switch/test nodes.
  • Verified representative signal, power, switch, SGND, and GND pins; no missing parametric metadata was surfaced by the project index or review checks.
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
GND
A1
Power Out
Ground
Ground
Bottom
50
LTM4712IY-PBF_1_1
Power ground
GND
A2
Power Out
Ground
Ground
Bottom
50
LTM4712IY-PBF_1_1
Power ground
ISN
A3
Input
Analog
Current Sense
Left
20
LTM4712IY-PBF_1_1
Average current sense negative
ISP
A4
Input
Analog
Current Sense
Left
20
LTM4712IY-PBF_1_1
Average current sense positive
IMON
A5
Output
Analog
Current Sense
Right
20
LTM4712IY-PBF_1_1
Current monitor output
CLKOUT
A6
Output
Clock
Synchronization
Right
30
LTM4712IY-PBF_1_1
Synchronization clock output
FREQ
A7
Input
Clock
Frequency Control
Left
30
LTM4712IY-PBF_1_1
Switching frequency set
PGOOD
A8
Output
Control
Status
Right
40
LTM4712IY-PBF_1_1
Open-drain power good output
PHMODE
A9
Input
Control
Mode Control
Left
40
LTM4712IY-PBF_1_1
Clock phase mode select
MODE
A10
Input
Control
Mode Control
Left
40
LTM4712IY-PBF_1_1
FCM pulse-skipping select
SS
A11
Input
Control
Soft Start
Left
40
LTM4712IY-PBF_1_1
Soft-start capacitor input
GND
A12
Power Out
Ground
Ground
Bottom
50
LTM4712IY-PBF_1_1
Power ground
GND
B1
Power Out
Ground
Ground
Bottom
50
LTM4712IY-PBF_1_1
Power ground
GND
B2
Power Out
Ground
Ground
Bottom
50
LTM4712IY-PBF_1_1
Power ground
INTVCC
B3
Power Out
Power
Bias Supply
Top
10
LTM4712IY-PBF_1_1
Internal 5V regulator output
EXTVCC
B4
Power In
Power
Bias Supply
Top
10
LTM4712IY-PBF_1_1
External LDO supply input
ISET
B5
Input
Analog
Current Limit
Left
20
LTM4712IY-PBF_1_1
Average current limit set
SYNC
B6
Input
Clock
Synchronization
Left
30
LTM4712IY-PBF_1_1
External synchronization input
SGND
B7
Power Out
Ground
Ground
Bottom
50
LTM4712IY-PBF_1_1
Signal ground
RUN
B8
Input
Control
Enable
Left
40
LTM4712IY-PBF_1_1
Enable control input
FB
B9
Input
Analog
Feedback
Left
20
LTM4712IY-PBF_1_1
Error amplifier feedback input
COMPa
B10
Passive
Analog
Compensation
Left
20
LTM4712IY-PBF_1_1
Compensation amplifier node
COMPb
B11
Passive
Analog
Compensation
Left
20
LTM4712IY-PBF_1_1
Internal compensation node

LTM4712IY#PBF