Part Datasheet and Footprint Verification

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Here’s a complete execution of your 4 requested steps for the part project ESP32-S3R16V.
  1. Review of available part information in the project
  • MPN: ESP32-S3R16V
  • Manufacturer: Espressif
  • Part type: Integrated Circuits
  • Designator prefix: IC
  • Datasheet property: Present — Datasheet
  • Package: Not explicitly set in properties (symbol and footprint exist)
  • Symbol pins present: 57 total (numbered 1..57), including LNA_IN (Pin 1), dual VDD3P3_1/VDD3P3_2 (Pins 2/3), CHIP_PU (Pin 4), and GND (Pin 57).
  • Footprint: Present with pad names matching symbol pins (pads include LNA_IN, GPIOx, SPIx, VDDA_1/2, GND, etc.)
  1. Datasheet URL check and update
  • Datasheet already set: Datasheet
  • No change required.
  1. Datasheet scan — extracted metadata
Absolute Maximum Ratings

Table

ParameterDescriptionMinMaxUnit
Input power pinsAllowed input voltage–0.33.6V
IoutputCumulative IO output current—1500mA
TSTOREStorage temperature–40150°C
Recommended Operating Conditions

Table

ParameterDescriptionMinTypMaxUnitNotes
VDDA, VDD3P3Recommended input voltage3.03.33.6V1
VDD3P3_RTCRecommended input voltage3.03.33.6V2
VDD_SPI (as input)——1.8 / 3.33.6V2
VDD3P3_CPURecommended input voltage3.03.33.6V3
IVDDCumulative input current0.5——A4
VDD_SPI Internal/Output Characteristics

Table

ParameterDescriptionTypUnitNotes
RSPIVDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM14Ω2
ISPIOutput current when VDD_SPI powered by 1.8 V Flash Voltage Regulator40mA—
DC Characteristics (3.3 V, 25 °C)

Table

ParameterDescriptionMinTypMaxUnit
CINPin capacitance—2—pF
VIHHigh-level input voltage0.75 × VDD—VDD + 0.3V
VILLow-level input voltage–0.3—0.25 × VDDV
VIL_nRSTCHIP_PU reset voltage–0.3—0.25 × VDDV
ADC Characteristics

Table

ParameterDescriptionMinMaxUnit
DNLDifferential nonlinearity–44LSB
INLIntegral nonlinearity–88LSB
Sampling rate——100 kSPS—
Current Consumption (3.3 V, 25 °C, peaks/typicals per tables)

Table

ModeConditionValue
Wi‑Fi TX802.11b, 1 Mbps, @21 dBm340 mA (peak)
Wi‑Fi TX802.11g, 54 Mbps, @19 dBm291 mA (peak)
Wi‑Fi TX802.11n, HT20, MCS7, @18.5 dBm283 mA (peak)
Wi‑Fi TX802.11n, HT40, MCS7, @18 dBm286 mA (peak)
Wi‑Fi RX802.11b/g/n, HT2088 mA (peak)
Wi‑Fi RX802.11n, HT4091 mA (peak)
BLE TX@ 21.0 dBm335 mA (peak)
BLE TX@ 9.0 dBm193 mA (peak)
BLE TX@ 0 dBm176 mA (peak)
BLE TX@ –15.0 dBm116 mA (peak)
BLE RX—93 mA (peak)
Light‑sleepVDD_SPI/Wi‑Fi off, GPIOs Hi‑Z240 µA (typ)
Deep‑sleepRTC mem + peripherals on8 µA (typ)
Deep‑sleepRTC mem on, peripherals off7 µA (typ)
Power offCHIP_PU low1 µA (typ)
Pin Overview (per Table 2-1)

Table

RangeNotable pins in range
1–4LNA_IN(1), VDD3P3(2,3), CHIP_PU(4)
5–18GPIO0..GPIO13
19–27GPIO14, VDD3P3_RTC(20), XTAL_32K_P/N(21/22), GPIO17..GPIO21
28–37SPICS1(28), VDD_SPI(29), SPIHD/WP/CS0/CLK/Q/D(30–35), SPICLK_N/P(36/37)
38–46GPIO33..GPIO38, MTCK(44), MTDO(45), VDD3P3_CPU(46)
47–52MTDI(47), MTMS(48), U0TXD(49), U0RXD(50), GPIO45(51), GPIO46(52)
53–57XTAL_N(53), XTAL_P(54), VDDA(55,56), GND(57, exposed pad)
Strapping Pins (default states)

Table

PinDefault
GPIO0Weak pull‑up (1)
GPIO3Floating
GPIO45Weak pull‑down (0)
GPIO46Weak pull‑down (0)
Variant details (Table 1-1)

Table

PartIn‑package FlashIn‑package PSRAMAmbient tempVDD_SPIChip rev
ESP32‑S3R16V—16 MB (Octal SPI)–40 ∼ 65 °C1.8 Vv0.2
Wi‑Fi / Bluetooth LE features
  • Wi‑Fi: 802.11b/g/n; HT20/HT40; MCS0‑7; data rate up to 150 Mbps; RX STBC; adjustable TX power; antenna diversity with external RF switch.
  • Bluetooth LE: Bluetooth 5 + Mesh; PHYs: 1M, 2M, Coded (125/500 kbps); Class 1 TX power; LE Advertising Extensions; multiple sets; simultaneous advertising and scanning.
Package and mechanical
  • Package: QFN56 (7×7 mm), exposed ground pad present (datasheet Figure 7‑1).
  • Thermal pad guidance: connect EPAD to ground with at least nine ground vias; use paste windowing as recommended.
RF/LNA_IN guidance
  • 50 Ω controlled‑impedance RF trace, CLC matching near the chip; use 0201 parts; stub on first capacitor to suppress harmonics; include antenna ESD.
Crystals
  • Main crystal: 40 MHz only; include ~24 nH series element on XTAL_P initially; tune C1/C4 per CL formula.
  • 32.768 kHz RTC crystal optional; ESR ≤ 70 kΩ; bias resistor 5 MΩ < R ≤ 10 MΩ if needed.
  1. Cross‑check: symbol and footprint vs datasheet
Symbol integrity
  • Pin count: Symbol contains 57 pins (1..57) including the exposed pad GND as Pin 57 — matches QFN56 + EPAD in the datasheet.
  • Naming and numbering: Spot‑checks align with Table 2‑1 — e.g., LNA_IN = Pin 1, VDD3P3_1 = Pin 2, CHIP_PU = Pin 4, VDD_SPI = Pin 29, SPI bus pins (30–35), SPICLK_N/P (36/37), VDD3P3_CPU = Pin 46, U0TXD/U0RXD = Pins 49/50, VDDA_1/VDDA_2 = Pins 55/56, GND = Pin 57.
  • Result: No symbol mismatches found.
Footprint integrity
  • Pad coverage: Footprint includes pads named for all symbol pins, including an EPAD labeled GND — consistent with datasheet requirement for an exposed ground pad.
  • Mechanical dimensions: The footprint data exposed to the tool does not include pad pitch/size or body size; thus, I cannot verify QFN56 7×7 mm outline, pin‑1 orientation marker, or pad pitch against the datasheet drawing.
  • Thermal viaing: Datasheet calls for “at least nine” ground vias in the EPAD; via stitching cannot be verified from the available footprint metadata.
Flags and recommendations
  • Missing/uncertain: Package properties are not explicitly set in the part metadata; consider setting “QFN56, 7×7 mm” to avoid ordering ambiguity.
  • Verification needed: Manually confirm in the Footprint editor that:
    • Body size is 7×7 mm and matches the ESP32‑S3 QFN56 land pattern.
    • Pin pitch and pad dimensions match the datasheet’s QFN56 drawing.
    • Pin‑1 marker and pad numbering around the perimeter follow the datasheet orientation.
    • EPAD solder paste windowing and via‑in‑pad/thermal vias follow the recommendations (≥ 9 vias tied to GND).
  • Electrical variant note: For ESP32‑S3R16V, VDD_SPI domain is 1.8 V (per Table 1‑1). Ensure any reference designs and net annotations reflect 1.8 V for in‑package PSRAM/flash operation.
If you want, I can proceed to add the missing package property and prepare a short checklist for verifying the footprint dimensions against the datasheet land pattern.
Run ERC/DRC checks
Verify pin-1 orientation
Add package metadata
Check RF matching guidance
Sign up to send

Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Part Type
Terminal Order
LNA_IN
1
Unspecified
Terminal
VDD3P3_1
2
Unspecified
Terminal
VDD3P3_2
3
Unspecified
Terminal
CHIP_PU
4
Unspecified
Terminal
GPIO0
5
Unspecified
Terminal
GPIO1
6
Unspecified
Terminal
GPIO2
7
Unspecified
Terminal
GPIO3
8
Unspecified
Terminal
GPIO4
9
Unspecified
Terminal
GPIO5
10
Unspecified
Terminal
GPIO6
11
Unspecified
Terminal
GPIO7
12
Unspecified
Terminal
GPIO8
13
Unspecified
Terminal
GPIO9
14
Unspecified
Terminal
GPIO10
15
Unspecified
Terminal
GPIO11
16
Unspecified
Terminal
GPIO12
17
Unspecified
Terminal
GPIO13
18
Unspecified
Terminal
GPIO14
19
Unspecified
Terminal
VDD3P3_RTC
20
Unspecified
Terminal
XTAL_32K_P
21
Unspecified
Terminal
XTAL_32K_N
22
Unspecified
Terminal
GPIO17
23
Unspecified
Terminal

ESP32-S3R16V