Part Metadata Review and Update
Table
| Field | Status | Notes |
|---|---|---|
| Manufacturer Part Number | Present | CA3046 |
| Manufacturer Name | Missing | Datasheet source indicates Intersil lineage for the reviewed sheet |
| Designator Prefix | Present | U |
| Datasheet URL | Added | Now set |
| Package property | Missing as project property | But project assets indicate DIP14_300_LIT footprint and STEP model |
Table
| Item | Value |
|---|---|
| Device type | General-purpose NPN transistor array |
| Internal structure | 5 NPN transistors total |
| Special topology | 1 differential pair + 3 isolated transistors |
| Package family in reviewed sheet | 14-lead PDIP and 14-lead SOIC |
| Absolute max VCEO | 15 V |
| Absolute max VCBO | 20 V |
| Absolute max collector current | 50 mA per transistor |
| Max power dissipation | 300 mW per transistor |
| Typical transition frequency | 550 MHz typ |
| Max junction temperature | 150 C |
| Storage temperature | -65 C to 150 C |
Table
| Check | Result | Notes |
|---|---|---|
| Pin count | Pass | Symbol has 14 terminals, matching the datasheet requirement to match pin count exactly |
| Pin numbering | Pass | Pins 1-14 are present |
| Functional grouping | Mostly pass | The terminal naming pattern matches the CA3046 structure: Q1/Q2 pair plus Q3/Q4/Q5 isolated devices |
| Pin descriptions | Flag | No Pin Description properties are populated |
| Pin types | Flag | All terminals are currently Unspecified |
| Symbol clarity | Minor flag | Pin 3 is labeled E, which is probably the common emitter node of the differential pair, but the label is a bit ambiguous without a description |
Table
| Check | Result | Notes |
|---|---|---|
| Package family | Likely pass | Project assets indicate DIP14_300_LIT, which is consistent with a 14-lead PDIP |
| Pad count | Likely pass | The project has 14 corresponding pad/terminal names |
| Full dimensional verification | Incomplete | I can confirm package family/count alignment, but I did not get enough geometric detail from the current layout data to verify every pad dimension and spacing numerically |
Table
| Issue | Severity | Details |
|---|---|---|
| Missing Manufacturer Name | Medium | Should be filled from the chosen datasheet source |
| Missing package metadata property | Medium | Footprint exists, but no explicit package property is set |
| All terminal Pin Types are Unspecified | High | ERC usefulness is reduced |
| No Pin Descriptions | Medium | The symbol is usable, but not self-documenting |
| No section/group/orientation metadata | Low | Not required for a simple 14-pin part, but still useful |
CA3046