Part Metadata Review and Verification

flux

1. Part review Available part metadata

Table

FieldValue
MPNBQ25773REER
ManufacturerTexas Instruments
DescriptionBattery Management IC, 2-cell to 5-cell NVDC dual-phase buck-boost battery charge controller with system power monitor
DatasheetPDF
Project package propertyTO
Datasheet packageREE (WQFN, 36)
Datasheet body size4.00 mm x 5.00 mm
Datasheet max height0.8 mm
Symbol terminal count in project37
Footprint pad count in project37
3D modelPresent
Symbol/footprint structure found in the part project
  • The symbol contains 37 terminals: 36 numbered pins + 1 exposed pad.
  • The footprint contains 37 pads: 36 perimeter pads + 1 large center pad.
  • The center pad is assigned to PGND, which matches the datasheet’s Bottom pad (PGND) requirement.
2. Datasheet property check
  • A datasheet URL is already set on the part.
  • Because it already exists, no web search or property update was needed.
3. Datasheet metadata summary Device summary

Table

CategorySummary
Device typeSynchronous NVDC buck-boost battery charge controller
Battery support2-cell to 5-cell
Input source supportUSB adapter, USB-C PD SPR, USB-C PD EPR, traditional adapters
Input operating range3.5 V to 40 V
Charge currentUp to 16.3 A / 30 A based on 5 mOhm / 2 mOhm sense resistor
Input current limitUp to 8.2 A / 16.4 A based on 10 mOhm / 5 mOhm sense resistor
OTG3 V to 5 V, up to 3 A based on 10 mOhm sense resistor
Switching frequency600 kHz / 800 kHz programmable
InterfaceI2C
ADCIntegrated 16-bit ADC
Accuracy±0.5% charge voltage regulation, ±2% charge current regulation, ±2% input current regulation, ±2% input/charge current monitor
Special features

Table

FeatureNotes
NVDC architectureSystem stays regulated and can keep operating even if battery is discharged or removed
Quasi dual phase buck-boostSeamless transition between buck, buck-boost, and boost
Pass Through ModeClaimed >99% efficiency
DRSSDual random spread spectrum for EMI performance
ICOInput Current Optimizer
FRSIntegrated Fast Role Swap for USB-PD
Intel platform supportIMVP8 / IMVP9 features including VAP and PROCHOT behavior
PSYSSystem power monitor output
ProtectionThermal regulation, thermal shutdown, input/system/battery OVP, MOSFET and inductor OCP
Absolute maximum ratings

Table

ParameterRange
ACN_A, ACP_A, ACN_B, ACP_B, VBUS, VSYS-0.3 V to 45 V
SW1_A, SW1_B, SW2-2 V to 45 V
SRN, SRP-0.3 V to 30 V
BATDRV-0.3 V to 35 V
BTST1_A, BTST1_B, HIDRV1_A, HIDRV1_B-0.3 V to 50 V
BTST2, HIDRV2-0.3 V to 50 V
LODRV1_A, LODRV1_B, LODRV2 (25 ns)-4 V to 5.5 V
HIDRV1_A, HIDRV1_B (25 ns)-4 V to 50 V
HIDRV2 (25 ns)-4 V to 50 V
SW1_A, SW1_B (25 ns)-4 V to 45 V
SW2 (25 ns)-4 V to 45 V
SDA, SCL, REGN_A, REGN_B, CHRG_OK, CELL_BATPRES, ILIM_HIZ, LODRV1_A, LODRV1_B, LODRV2, CMPIN_TR, CMPOUT, MODE, EN_OTG-0.3 V to 5.5 V
/PROCHOT-0.3 V to 5.5 V
IADPT, IBAT, PSYS-0.3 V to 3.6 V
BTST1_A-SW1_A, BTST1_B-SW1_B, BTST2-SW2, HIDRV1_A-SW1_A, HIDRV1_B-SW1_B, HIDRV2-SW2, BATDRV-SRP-0.3 V to 5.5 V
SRP-SRN, ACP_A-ACN_A, ACP_B-ACN_B-0.3 V to 0.3 V
Junction temperature-40 C to 150 C
Storage temperature-55 C to 150 C
Recommended operating conditions

Table

ParameterRange
ACP_A, ACN_A, ACP_B, ACN_B, VBUS0 V to 40 V
VSYS0 V to 23 V
SRP, SRN0 V to 23 V
SW1_A, SW1_B-2 V to 40 V
SW2-2 V to 23 V
BTST1_A, BTST1_B, HIDRV1_A, HIDRV1_B0 V to 45 V
BTST2, HIDRV2, BATDRV0 V to 28 V
SDA, SCL, REGN_A, REGN_B, CHRG_OK, CELL_BATPRES, ILIM_HIZ, LODRV1_A, LODRV1_B, LODRV2, CMPIN_TR, CMPOUT, MODE, EN_OTG0 V to 5.3 V
/PROCHOT0 V to 5 V
IADPT, IBAT, PSYS0 V to 3.3 V
Differential: BTSTx-SWx, HIDRVx-SWx, BATDRV-SRP0 V to 5 V
Differential: SRP-SRN, ACP_A-ACN_A, ACP_B-ACN_B-0.2 V to 0.2 V
Junction temperature-40 C to 125 C
Selected electrical characteristics extracted

Table

ParameterValue
Input voltage operating range3.5 V to 40.00 V
System voltage regulation range5.16 V to 23.16 V
Charge current regulation accuracy-1.5% to 1.5%
REGN overvoltage falling threshold5.10 V / 5.30 V / 5.50 V min/typ/max
HIZ battery-powered current1000 uA / 1150 uA typ/max
PSYS gain accuracy-3.5% to 2%
PSYS clamp voltage3.1 V / 3.3 V
System OVP rising threshold, 2s11.85 V / 12.15 V / 12.35 V
System OVP rising threshold, 3s16.8 V / 17.15 V / 17.4 V
System OVP rising threshold, 4s21.90 V / 22.3 V / 22.60 V
Comparator threshold1.18 V / 1.2 V / 1.23 V
EN_OTG low input0.8 V
EN_OTG high input1.35 V
I2C low input threshold0.42 V
Package metadata

Table

FieldValue
Orderable partBQ25773REER
StatusActive Production
PackageWQFN (REE)
Pin count36 pins
Body size4.00 mm x 5.00 mm
Height0.8 mm max
Lead finishNIPDAU
MSLLevel-1-260C-UNLIM
Operating temperature-40 C to 125 C
Part markingBQ25773
Package dimensions extracted

Table

DimensionValue
Body A3.9 mm to 4.1 mm
Body B4.9 mm to 5.1 mm
Max height0.8 mm
Lead width0.15 mm to 0.25 mm
Lead length0.3 mm to 0.5 mm
Pin pitch0.4 mm
Thermal pad2.6 mm to 2.8 mm
Datasheet land-pattern exposed pad3.6 mm x 2.8 mm
Pin descriptions

Table

PinProject terminalDatasheet description
1LODRV1_ABuck phase A low-side MOSFET driver output
2REGN_A5 V LDO output for gate drive; requires 2.2 uF or 3.3 uF ceramic capacitor to power ground
3BTST1_ABootstrap supply for phase A high-side driver; connect 0.1 uF between SW1_A and BTST1_A
4HIDRV1_ABuck phase A high-side MOSFET driver
5SW1_ABuck phase A switching node
6VBUSCharger input voltage; recommends 1 ohm + 0.47 uF min input low-pass filter
7ACN_BPhase B input current-sense negative input; RC filter required
8ACP_BPhase B input current-sense positive input; RC filter required
9ACN_APhase A input current-sense negative input; RC filter required
10ACP_APhase A input current-sense positive input; RC filter required
11CHRG_OKOpen-drain status output; use 10 kOhm pullup
12EN_OTGActive-high OTG / VAP / FRS enable input
13ILIM_HIZInput current-limit programming pin via resistor divider
14IADPTAdapter current monitor output
15IBATBattery current monitor output
16MODEOperation mode pin; pull-down resistor required
17PSYSSystem power monitor output; resistor to ground generates voltage; clamp near 3.2 V
18~PROCHOTActive-low open-drain processor hot output
19SDAI2C data, open-drain; use 10 kOhm pullup
20SCLI2C clock input; use 10 kOhm pullup
21CMPOUTOpen-drain comparator output
22CMPIN_TRComparator input / temperature regulation input; tie to ground if unused
23CELL_BATPRESCell-count and battery-present pin via resistor divider; no external capacitor allowed
24SRNBattery current-sense negative input and battery voltage sense; use 0.1 uF filter cap across sense resistor and 10 ohm contact resistor
25SRPBattery current-sense positive input; use 0.1 uF filter cap across sense resistor
26BATDRVBATFET gate driver output
27VSYSCharger system voltage sense
28SW2Boost switching node
29HIDRV2Boost high-side MOSFET driver
30BTST2Bootstrap supply for boost high-side driver; connect 0.1 uF between SW2 and BTST2
31LODRV2Boost low-side MOSFET driver
32REGN_B5 V LDO output; internally connected to REGN_A; requires 2.2 uF or 3.3 uF capacitor
33LODRV1_BBuck phase B low-side MOSFET driver
34BTST1_BBootstrap supply for phase B high-side driver; connect 0.1 uF between SW1_B and BTST1_B
35HIDRV1_BBuck phase B high-side MOSFET driver
36SW1_BBuck phase B switching node
Exposed padPGNDCommon power ground thermal pad; must be soldered and tied into PGND with multiple vias
4. Symbol and footprint cross-check What matches

Table

CheckResult
Pin namingLooks consistent between symbol and footprint
Pin numberingLooks consistent for the pins sampled against the datasheet
Total connection countLooks consistent: 36 pins + exposed pad
Exposed pad functionLooks consistent: center pad is mapped to PGND
Package family / sizeLooks broadly consistent with a 4 mm x 5 mm WQFN with exposed pad
Mismatches / risks

Table

SeverityIssueWhy it matters
HighThe project property Package or Case Code = TO does not match the datasheet package REE (WQFN, 36)This can cause incorrect ordering metadata, bad library search matches, or confusion during manufacturing handoff
MediumThe footprint uses a center pad around 2.8 mm x 3.8 mm, while the datasheet extracts indicate thermal-pad related dimensions of 2.6 mm to 2.8 mm for package pad and 3.6 mm x 2.8 mm for land patternThis should be manually verified because exposed-pad geometry directly affects soldering, thermal performance, and assembly yield
MediumThe footprint asset naming implies a generic 37-pad QFN pattern rather than explicitly the TI REE0036A package codeIt may still be correct, but it increases the chance of an almost-right footprint being used for the wrong package revision
MediumThe datasheet explicitly requires the exposed pad to be soldered and tied into PGND with multiple viasIf the final footprint or recommended layout omits via-ready thermal strategy, the device may suffer thermal and mechanical reliability issues
Bottom line
  • Symbol: no obvious pin-name or pin-count problem found.
  • Footprint: mostly plausible, but the package metadata is definitely wrong and the exposed-pad / land-pattern dimensions should be verified against TI REE0036A before release.
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Files

Pins

Symbol

Layout

Preview

Name
Pin #
Type
Part Type
Terminal Order
LODRV1_A
1
Unspecified
Terminal
REGN_A
2
Unspecified
Terminal
BTST1_A
3
Unspecified
Terminal
HIDRV1_A
4
Unspecified
Terminal
SW1_A
5
Unspecified
Terminal
VBUS
6
Unspecified
Terminal
ACN_B
7
Unspecified
Terminal
ACP_B
8
Unspecified
Terminal
ACN_A
9
Unspecified
Terminal
ACP_A
10
Unspecified
Terminal
CHRG_OK
11
Unspecified
Terminal
EN_OTG
12
Unspecified
Terminal
ILIM_HIZ
13
Unspecified
Terminal
IADPT
14
Unspecified
Terminal
IBAT
15
Unspecified
Terminal
MODE
16
Unspecified
Terminal
PSYS
17
Unspecified
Terminal
~PROCHOT
18
Unspecified
Terminal
SDA
19
Unspecified
Terminal
SCL
20
Unspecified
Terminal
CMPOUT
21
Unspecified
Terminal
CMPIN_TR
22
Unspecified
Terminal
CELL_BATPRES
23
Unspecified
Terminal

BQ25773REER