Part Metadata Audit and Updates

flux

Fixed and verified.
Changes made:
  • Renamed pins:
    • PMID_GD → PG
    • ILIM/D- → D-
    • TS_BIAS/D+ → D+
  • Added TI datasheet-based pin descriptions for all 18 terminals.
  • Updated pin types using valid Flux ERC categories:
    • Power pins mapped to Power In, Power Out, or Ground
    • Open-drain outputs mapped to Open Collector
    • SDA/D+/D- mapped to Bi-Directional
    • Control pins mapped to Input
The terminal review checks now return no issues.
A

adrian95

Please also create the parametric symbol and place each pin into the correct section based on the datasheet.

flux

I’ll convert the symbol metadata to a parametric-style organization and assign each terminal to functional sections from the TI pin table, then verify the result.

flux

Done. I set all 18 terminals to Symbol Style: Parametric and assigned datasheet-based sections:
  • Power: BTST, REGN, BAT, SYS, SW, PMID, VBUS
  • Ground: GND
  • Communication: D+, D-, SDA, SCL
  • Analog: TS
  • Control: PG, STAT, ~INT, ~CE, ~QON
I also added pin groups, orientations, and terminal order values, then verified the part review checks return no issues.
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Files

Pins

Symbol

Layout

3D View

GND
PG
~INT
D-
~CE
PMID
~QON
REGN
STAT
SYS
SCL
SW
VBUS
BTST
BAT
D+
TS
SDA
Name
Pin #
Type
Part Type
Pin Description
Pin Group
BTST
1
Power In
Terminal
High-side switching MOSFET gate driver power supply; connect 47 nF bootstrap capacitor from BTST to SW.
Power
REGN
2
Power Out
Terminal
Internal charger linear regulator output; connect 4.7 uF ceramic capacitor from REGN to power ground close to IC.
Power
PG
3
Open Collector
Terminal
Open-drain active-low power-good indicator; pull up with 10 kΩ to logic rail.
Control Bus
D-
4
Bi-Directional
Terminal
USB D- analog I/O for BC1.2 host/charging-port detection.
USB
D+
5
Bi-Directional
Terminal
USB D+ analog I/O for BC1.2 host/charging-port detection.
USB
TS
6
Input
Terminal
Battery temperature qualification analog input; connect NTC divider from REGN bias to TS to GND.
Analog
~QON
7
Input
Terminal
BATFET enable or system power reset digital input; internal pull-up, active low for ship-mode exit/reset control.
Control Bus
BAT
8
Power In
Terminal
Battery charging power connection; connect to positive terminal of single-cell battery pack.
Power
SYS
9
Power Out
Terminal
Charger system output / buck converter output; internal BATFET connects SYS to BAT.
Power
STAT
10
Open Collector
Terminal
Open-drain charge status output; pull up with 10 kΩ or leave floating if unused.
Control Bus
~INT
11
Open Collector
Terminal
Open-drain interrupt output; active-low 256 us pulse for charger status/fault reporting, pull up with 10 kΩ.
Control Bus
SDA
12
Bi-Directional
Terminal
I2C interface data; pull up to logic rail with 10 kΩ.
I2C
SCL
13
Input
Terminal
I2C interface clock; pull up to logic rail with 10 kΩ.
I2C
~CE
14
Input
Terminal
Active-low charge enable digital input; must be tied high or low, do not leave floating.
Control Bus
GND
15
Ground
Terminal
Ground return.
Ground
SW
16
Power Out
Terminal
Switching node connected to output inductor; connect 47 nF bootstrap capacitor from SW to BTST.
Power
PMID
17
Power In
Terminal
Input power intermediate node / HSFET drain connection; internal reverse-block MOSFET connects VBUS to PMID.
Power
VBUS
18
Power In
Terminal
Charger input voltage pin; internal reverse-block MOSFET source connection.
Power

BQ25620RYKR