Part Metadata Audit and Updates

flux

Fixed and verified.
Changes made:
  • Renamed pins:
    • PMID_GD → PG
    • ILIM/D- → D-
    • TS_BIAS/D+ → D+
  • Added TI datasheet-based pin descriptions for all 18 terminals.
  • Updated pin types using valid Flux ERC categories:
    • Power pins mapped to Power In, Power Out, or Ground
    • Open-drain outputs mapped to Open Collector
    • SDA/D+/D- mapped to Bi-Directional
    • Control pins mapped to Input
The terminal review checks now return no issues.
A

adrian95

Please also create the parametric symbol and place each pin into the correct section based on the datasheet.

flux

I’ll convert the symbol metadata to a parametric-style organization and assign each terminal to functional sections from the TI pin table, then verify the result.

flux

Done. I set all 18 terminals to Symbol Style: Parametric and assigned datasheet-based sections:
  • Power: BTST, REGN, BAT, SYS, SW, PMID, VBUS
  • Ground: GND
  • Communication: D+, D-, SDA, SCL
  • Analog: TS
  • Control: PG, STAT, ~INT, ~CE, ~QON
I also added pin groups, orientations, and terminal order values, then verified the part review checks return no issues.
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
BTST
1
Power In
Power
Power
Top
1
High-side switching MOSFET gate driver power supply; connect 47 nF bootstrap capacitor from BTST to SW.
REGN
2
Power Out
Power
Power
Top
2
Internal charger linear regulator output; connect 4.7 uF ceramic capacitor from REGN to power ground close to IC.
PG
3
Open Collector
Control
Control Bus
Right
3
Open-drain active-low power-good indicator; pull up with 10 kΩ to logic rail.
D-
4
Bi-Directional
Communication
USB
Left
4
USB D- analog I/O for BC1.2 host/charging-port detection.
D+
5
Bi-Directional
Communication
USB
Left
5
USB D+ analog I/O for BC1.2 host/charging-port detection.
TS
6
Input
Analog
Analog
Left
6
Battery temperature qualification analog input; connect NTC divider from REGN bias to TS to GND.
~QON
7
Input
Control
Control Bus
Left
7
BATFET enable or system power reset digital input; internal pull-up, active low for ship-mode exit/reset control.
BAT
8
Power In
Power
Power
Top
8
Battery charging power connection; connect to positive terminal of single-cell battery pack.
SYS
9
Power Out
Power
Power
Top
9
Charger system output / buck converter output; internal BATFET connects SYS to BAT.
STAT
10
Open Collector
Control
Control Bus
Right
10
Open-drain charge status output; pull up with 10 kΩ or leave floating if unused.
~INT
11
Open Collector
Control
Control Bus
Right
11
Open-drain interrupt output; active-low 256 us pulse for charger status/fault reporting, pull up with 10 kΩ.
SDA
12
Bi-Directional
Communication
I2C
Left
12
I2C interface data; pull up to logic rail with 10 kΩ.
SCL
13
Input
Communication
I2C
Left
13
I2C interface clock; pull up to logic rail with 10 kΩ.
~CE
14
Input
Control
Control Bus
Left
14
Active-low charge enable digital input; must be tied high or low, do not leave floating.
GND
15
Ground
Ground
Ground
Bottom
15
Ground return.
SW
16
Power Out
Power
Power
Top
16
Switching node connected to output inductor; connect 47 nF bootstrap capacitor from SW to BTST.
PMID
17
Power In
Power
Power
Top
17
Input power intermediate node / HSFET drain connection; internal reverse-block MOSFET connects VBUS to PMID.
VBUS
18
Power In
Power
Power
Top
18
Charger input voltage pin; internal reverse-block MOSFET source connection.

BQ25620RYKR