Function Generator PCB Design
Thought
Work done
- PCB size reduced to 90 mm × 65 mm.
- Added and connected test points:
Tasks not executed (requires manual action)
- Configure bottom copper layer as a solid GND pour with thermal relief.
- Implement stitching vias and guard polygon around U6 output.
- Re-route analog nets (ANALOG_IN, RAW_POS, RAW_NEG) for shortest, isolated paths.
- Widen +12 V, −12 V, +5 V traces to ≥1.0 mm.
- Re-pour all copper polygons and verify stitching via coverage.
- Re-position U5, U6, J4 inline, and group U4, J2, J3 away from analog.
- Add silkscreen labels on critical connectors:
- Run ERC/DRC checks and regenerate the routed 2-layer PCB.
Success Criteria Review
- Bottom ground pour & guard polygon: ❌ not in place.
- Power trace widths ≥1.0 mm: ❌ not widened.
- Analog net re-routing: ❌ not updated.
- PCB size reduction: ✅ achieved.
- Silkscreen labels & test points: test points placed ✅, labels missing ❌.
- DRC/ERC pass & PCB regeneration: ❌ not done.
Recommended next steps
Proceed to implement the ground pour, stitching vias, guard polygon, power-trace widening, and analog-net re-routing in the PCB layout. Then add silkscreen labels, run ERC/DRC, re-pour polygons, and regenerate the routed board to complete the improvements.
